From fb3265b371a141c4ffc97dcf8cc66e090c516dc8 Mon Sep 17 00:00:00 2001
From: Sudakshina Das <sudi.das@arm.com>
Date: Mon, 12 Nov 2018 13:09:55 +0000
Subject: [BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory
 Tagging Extension

This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.

This patch add support to the Tag setting instructions from
MTE which consists of the following instructions:
- STG [<Xn|SP>, #<simm>]
- STG [<Xn|SP>, #<simm>]!
- STG [<Xn|SP>], #<simm>
- STZG [<Xn|SP>, #<simm>]
- STZG [<Xn|SP>, #<simm>]!
- STZG [<Xn|SP>], #<simm>
- ST2G [<Xn|SP>, #<simm>]
- ST2G [<Xn|SP>, #<simm>]!
- ST2G [<Xn|SP>], #<simm>
- STZ2G [<Xn|SP>, #<simm>]
- STZ2G [<Xn|SP>, #<simm>]!
- STZ2G [<Xn|SP>], #<simm>
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!
- STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm>

where
<Xn|SP> : Is the 64-bit GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range -4096 to 4080, defaulting to 0.

*** include/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
	and AARCH64_OPND_ADDR_SIMM13.
	(aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.

*** opcodes/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
	for AARCH64_OPND_QLF_imm_tag.
	(operand_general_constraint_met_p): Add case for
	AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
	(aarch64_print_operand): Likewise.
	* aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
	(aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
	for both offset and pre/post indexed versions.
	(AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

*** gas/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (parse_operands): Add switch case for
	AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
	(fix_insn): Likewise.
	(warn_unpredictable_ldst): Exempt STGP.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g,
	stzg, stz2g and stgp.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
---
 opcodes/ChangeLog | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

(limited to 'opcodes/ChangeLog')

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 424368c..df21eeb 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,20 @@
 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
 
+	* aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
+	for AARCH64_OPND_QLF_imm_tag.
+	(operand_general_constraint_met_p): Add case for
+	AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
+	(aarch64_print_operand): Likewise.
+	* aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
+	(aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
+	for both offset and pre/post indexed versions.
+	(AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
+	* aarch64-asm-2.c: Regenerated.
+	* aarch64-dis-2.c: Regenerated.
+	* aarch64-opc-2.c: Regenerated.
+
+2018-11-12  Sudakshina Das  <sudi.das@arm.com>
+
 	* aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
 	* aarch64-asm-2.c: Regenerated.
 	* aarch64-dis-2.c: Regenerated.
-- 
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