From 4ebce1a0a5911e71aa2d00932ffb2126ff1f3633 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Tue, 20 Dec 2016 01:53:03 +0000 Subject: MIPS16/opcodes: Correct 64-bit macros' ISA membership Limit the DDIV, DDIVU, DREM, DREMU and DSUBU macros to the MIPS III rather than MIPS I ISA. These macros expand to machine code sequences including 64-bit instructions which require a 64-bit ISA. Entries for those instructions are already correctly marked, however the marking is ignored if entries are used in the process of macro expansion rather than directly, making it possible to indirectly produce 64-bit machine code even when output requested has been limited to a 32-bit ISA. opcodes/ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu" INSN_MACRO entries. gas/ * testsuite/gas/mips/mips16-macro.l: New list test. * testsuite/gas/mips/mips.exp: Run the new test. --- opcodes/ChangeLog | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'opcodes/ChangeLog') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4d5fae6..2890354 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,6 +1,12 @@ 2016-12-20 Maciej W. Rozycki * mips16-opc.c (mips16_opcodes): Set membership to I3 rather + than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu" + INSN_MACRO entries. + +2016-12-20 Maciej W. Rozycki + + * mips16-opc.c (mips16_opcodes): Set membership to I3 rather than I1 for the SP-relative "sd"/$ra entry (SDRASP minor opcode). -- cgit v1.1