From 3d68f91c0fb05b426e554004cabd3ded4c91f9c8 Mon Sep 17 00:00:00 2001 From: "Jose E. Marchesi" Date: Thu, 9 Oct 2014 13:16:53 +0100 Subject: This is a series of patches that add support for the SPARC M7 cpu to binutils. They were discussed and approved here: https://sourceware.org/ml/binutils/2014-10/msg00038.html --- opcodes/ChangeLog | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'opcodes/ChangeLog') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e5bcb13..b02424d 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,24 @@ +2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com> + + * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt', + `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'. + Annotate table with HWCAP2 bits. + Add instructions xmontmul, xmontsqr, xmpmul. + (sparc-opcodes): Add the `mwait', `wr r,r,%mwait', `wr + r,i,%mwait' and `rd %mwait,r' instructions. + Add rd/wr instructions for accessing the %mcdper ancillary state + register. + (sparc-opcodes): Add sparc5/vis4.0 instructions: + subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8, + fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8, + fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16, + fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8, + fpsubus16, and faligndatai. + * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28) + ancillary state register to the table. + (print_insn_sparc): Handle the %mcdper ancillary state register. + (print_insn_sparc): Handle new operand type '}'. + 2014-09-22 H.J. Lu * i386-dis.c (MOD_0F20): Removed. -- cgit v1.1