From 3a8547d2fb5319890dda877fb313822053083c3a Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Mon, 1 Jun 2015 09:51:28 +0200 Subject: x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand order As pointed out before, the documentation mandates the rounding mode to follow the GPR, so disassembler should produce output accordingly. gas/testsuite/ 2015-06-01 Jan Beulich * gas/i386/avx512f.s: Adjust operand order for Intel syntax vcvt{,u}si2ss. * gas/i386/x86-64-avx512f.s: Adjust operand order for Intel syntax vcvt{,u}si2s{d,s}. opcodes/ 2015-06-01 Jan Beulich * i386-dis.c (print_insn): Swap rounding mode specifier and general purpose register in Intel mode. --- opcodes/ChangeLog | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'opcodes/ChangeLog') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 648669c..4104df9 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2015-06-01 Jan Beulich + * i386-dis.c (print_insn): Swap rounding mode specifier and + general purpose register in Intel mode. + +2015-06-01 Jan Beulich + * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}. * i386-tbl.h: Regenerate. -- cgit v1.1