From 2c232b8361a044d689d12161b7a645d238586f5e Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Mon, 13 Mar 2017 12:46:33 -0700
Subject: RISC-V: Fix [dis]assembly of srai/srli

These were simple copy/paste errors from the compressed left shift
pattern, which can't have a 0-register.
---
 opcodes/ChangeLog | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'opcodes/ChangeLog')

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f9f2c04..622ccf4 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2017-03-13  Andrew Waterman  <andrew@sifive.com>
+
+	* riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
+	<srl> Likewise.
+	<srai> Likewise.
+	<sra> Likewise.
+
 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* i386-gen.c (opcode_modifiers): Replace S with Load.
-- 
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