From 12e35da62fbce831da2bb591e31d05aa4060d11a Mon Sep 17 00:00:00 2001 From: Przemyslaw Wirkus Date: Mon, 28 Sep 2020 15:49:11 +0100 Subject: This patch introduces ETMv4 (Embedded Trace Macrocell) system registers for the AArch64 architecture. gas * testsuite/gas/aarch64/etm-ro-invalid.d: New test. * testsuite/gas/aarch64/etm-ro-invalid.l: New test. * testsuite/gas/aarch64/etm-ro-invalid.s: New test. * testsuite/gas/aarch64/etm-ro.s: New test. * testsuite/gas/aarch64/etm-wo-invalid.d: New test. * testsuite/gas/aarch64/etm-wo-invalid.l: New test. * testsuite/gas/aarch64/etm-wo-invalid.s: New test. * testsuite/gas/aarch64/etm-wo.s: New test. * testsuite/gas/aarch64/etm.s: New test. * testsuite/gas/aarch64/sysreg.d: system register s2_1_c0_c3_0 disassembled now to trcstatr. opcodes * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn, TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1, TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET, TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1, TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R, TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4, TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12, TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3, TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn, TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn, TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR, TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR, TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn. --- opcodes/ChangeLog | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) (limited to 'opcodes/ChangeLog') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e9dfb78..c57c0b1 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,11 +1,28 @@ 2020-09-28 Przemyslaw Wirkus - * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR. + * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn, + TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1, + TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET, + TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1, + TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R, + TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4, + TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12, + TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR + WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3, + TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn, + TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn, + TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR, + TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR, + TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn. 2020-09-28 Przemyslaw Wirkus - * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 , - TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1. + * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR. + +2020-09-28 Przemyslaw Wirkus + + * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 , + TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1. 2020-09-26 Alan Modra -- cgit v1.1