From fa85fb9a1bf35209a149d07ebefb2a8970e4a27a Mon Sep 17 00:00:00 2001 From: Marcus Shawcroft Date: Tue, 15 Apr 2014 17:46:07 +0100 Subject: [AArch64] Fix off by one error in instruction relaxation mask. The AArch64 TLSDESC to IE relaxation code uses a bit mask intended to ensure that destination register in a relaxed ldr instruction is always X0. The mask has an off by one error resulting in the most significant bit of the destination register being retained in the relaxed instruction. The issue generally appears when the compiler emits TLS accesses code under high register pressure resulting in a broken code sequence. --- ld/testsuite/ChangeLog | 5 +++++ ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'ld/testsuite') diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog index e239ce8..ae0fa89 100644 --- a/ld/testsuite/ChangeLog +++ b/ld/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2014-04-15 Marcus Shawcroft + + * ld-aarch64/tls-relax-gdesc-ie.s (var): Adjust test case + to include all 5 bits of LDR destination register. + 2014-04-10 Senthil Kumar Selvaraj * ld-avr/norelax_diff.d: New testcase. diff --git a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s index c20690c..38b3721 100644 --- a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s +++ b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s @@ -4,7 +4,7 @@ var: .word 2 .text adrp x0, :tlsdesc:var - ldr x1, [x0, #:tlsdesc_lo12:var] + ldr x17, [x0, #:tlsdesc_lo12:var] add x0, x0, :tlsdesc_lo12:var .tlsdesccall var blr x1 -- cgit v1.1