From fbc95f1e11facf233e89a9c2b4dde06b9aaf4b86 Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng@sifive.com>
Date: Tue, 29 Jun 2021 14:36:35 +0800
Subject: RISC-V: Add PT_RISCV_ATTRIBUTES and add it to PHDR.

We added PT_RISCV_ATTRIBUTES to program header to make
.riscv.attribute easier to find in dynamic loader or kernel.

Ref:
https://github.com/riscv/riscv-elf-psabi-doc/pull/71

ChangeLog:

bfd/

	* elfnn-riscv.c(RISCV_ATTRIBUTES_SECTION_NAME): New.
	(riscv_elf_additional_program_headers): Ditto.
	(riscv_elf_modify_segment_map): Ditto.
	(elf_backend_additional_program_headers): Ditto.
	(elf_backend_modify_segment_map): Ditto.
	(elf_backend_obj_attrs_section): Use RISCV_ATTRIBUTES_SECTION_NAME
	rather than string literal.

binutils/

	* readelf.c(get_riscv_segment_type): New.
	(get_segment_type): Handle EM_RISCV.

include/

	* elf/riscv.h (PT_RISCV_ATTRIBUTES): New.
	* testsuite/ld-elf/orphan-region.ld: Discard .riscv.attributes
	section for simplify testcase.
	* testsuite/ld-riscv-elf/attr-phdr.d: New.
	* testsuite/ld-riscv-elf/attr-phdr.s: Ditto.
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Add attr-phdr to
	testcase.
---
 ld/testsuite/ld-riscv-elf/attr-phdr.d      | 19 +++++++++++++++++++
 ld/testsuite/ld-riscv-elf/attr-phdr.s      |  9 +++++++++
 ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp |  1 +
 3 files changed, 29 insertions(+)
 create mode 100644 ld/testsuite/ld-riscv-elf/attr-phdr.d
 create mode 100644 ld/testsuite/ld-riscv-elf/attr-phdr.s

(limited to 'ld/testsuite/ld-riscv-elf')

diff --git a/ld/testsuite/ld-riscv-elf/attr-phdr.d b/ld/testsuite/ld-riscv-elf/attr-phdr.d
new file mode 100644
index 0000000..43f2ea5
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-phdr.d
@@ -0,0 +1,19 @@
+#name: PT_RISCV_ATTRIBUTES check
+#source: attr-phdr.s
+#as: -march=rv32ic
+#ld: -m[riscv_choose_ilp32_emul]
+#readelf: -l
+
+Elf file type is EXEC \(Executable file\)
+Entry point .*
+There are .* program headers, starting at offset .*
+
+Program Headers:
+  Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
+  RISCV_ATTRIBUT .*
+  LOAD           .*
+
+ Section to Segment mapping:
+  Segment Sections...
+   00     .riscv.attributes 
+   01     .text 
diff --git a/ld/testsuite/ld-riscv-elf/attr-phdr.s b/ld/testsuite/ld-riscv-elf/attr-phdr.s
new file mode 100644
index 0000000..f075248
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-phdr.s
@@ -0,0 +1,9 @@
+	.attribute arch, "rv32i2p0_m2p0"
+	.option nopic
+	.text
+	.align	1
+	.globl	_start
+	.type	_start, @function
+_start:
+	ret
+	.size	_start, .-_start
diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index 1f1245a..1f6eceb 100644
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -112,6 +112,7 @@ if [istarget "riscv*-*-*"] {
     run_dump_test "attr-merge-priv-spec-failed-04"
     run_dump_test "attr-merge-priv-spec-failed-05"
     run_dump_test "attr-merge-priv-spec-failed-06"
+    run_dump_test "attr-phdr"
     run_ld_link_tests [list \
 	[list "Weak reference 32" "-T weakref.ld -m[riscv_choose_ilp32_emul]" "" \
 	    "-march=rv32i -mabi=ilp32" {weakref32.s} \
-- 
cgit v1.1