From 252dcdf432c67f6baafb766ed068c64db1eb2bad Mon Sep 17 00:00:00 2001 From: Alan Modra Date: Mon, 24 Aug 2020 16:32:57 +0930 Subject: PowerPC TPREL_HA/LO optimisation ppc64 ld optimises sequences like the following addis 3,13,wot@tprel@ha lwz 3,wot@tprel@l(3) to nop lwz 3,wot@tprel(13) when "wot" is located near enough to the thread pointer. However, the ABI doesn't require that R_PPC64_TPREL16_HA always be on an addis rt,13,imm instruction, and while ld checked for that on the high-part instruction it didn't disable the optimisation on the low-part instruction. This patch fixes that problem, disabling the tprel optimisation globally if high-part instructions don't pass sanity checks. The optimisation is also enabled for ppc32, where before ld.bfd had the code in the wrong place and ld.gold had it in a block only enabled for ppc64. bfd/ * elf32-ppc.c (ppc_elf_check_relocs): Set has_tls_reloc for high part tprel16 relocs. (ppc_elf_tls_optimize): Sanity check high part tprel16 relocs. Clear do_tls_opt on odd instructions. (ppc_elf_relocate_section): Move TPREL16_HA/LO optimisation later. Don't sanity check them here. * elf64-ppc.c (ppc64_elf_check_relocs): Set has_tls_reloc for high part tprel16 relocs. (ppc64_elf_tls_optimize): Sanity check high part tprel16 relocs. Clear do_tls_opt on odd instructions. (ppc64_elf_relocate_section): Don't sanity check TPREL16_HA. ld/ * testsuite/ld-powerpc/tls32.d: Update for TPREL_HA/LO optimisation. * testsuite/ld-powerpc/tlsexe32.d: Likewise. * testsuite/ld-powerpc/tlsldopt32.d: Likewise. * testsuite/ld-powerpc/tlsmark32.d: Likewise. * testsuite/ld-powerpc/tlsopt4_32.d: Likewise. * testsuite/ld-powerpc/tprel.s, * testsuite/ld-powerpc/tprel.d, * testsuite/ld-powerpc/tprel32.d: New tests. * testsuite/ld-powerpc/tprelbad.s, * testsuite/ld-powerpc/tprelbad.d: New test. * testsuite/ld-powerpc/powerpc.exp: Run them. gold/ * powerpc.cc (Target_powerpc): Add tprel_opt_ and accessors. (Target_powerpc::Scan::local): Sanity check tprel high relocs. (Target_powerpc::Scan::global): Likewise. (Target_powerpc::Relocate::relocate): Control tprel optimisation with tprel_opt_ and enable for 32-bit. --- ld/testsuite/ld-powerpc/powerpc.exp | 4 ++++ ld/testsuite/ld-powerpc/tls32.d | 40 ++++++++++++++++++------------------ ld/testsuite/ld-powerpc/tlsexe32.d | 32 ++++++++++++++--------------- ld/testsuite/ld-powerpc/tlsldopt32.d | 16 +++++++-------- ld/testsuite/ld-powerpc/tlsmark32.d | 8 ++++---- ld/testsuite/ld-powerpc/tlsopt4_32.d | 20 +++++++++--------- ld/testsuite/ld-powerpc/tprel.d | 12 +++++++++++ ld/testsuite/ld-powerpc/tprel.s | 10 +++++++++ ld/testsuite/ld-powerpc/tprel32.d | 13 ++++++++++++ ld/testsuite/ld-powerpc/tprelbad.d | 12 +++++++++++ ld/testsuite/ld-powerpc/tprelbad.s | 10 +++++++++ 11 files changed, 119 insertions(+), 58 deletions(-) create mode 100644 ld/testsuite/ld-powerpc/tprel.d create mode 100644 ld/testsuite/ld-powerpc/tprel.s create mode 100644 ld/testsuite/ld-powerpc/tprel32.d create mode 100644 ld/testsuite/ld-powerpc/tprelbad.d create mode 100644 ld/testsuite/ld-powerpc/tprelbad.s (limited to 'ld/testsuite/ld-powerpc') diff --git a/ld/testsuite/ld-powerpc/powerpc.exp b/ld/testsuite/ld-powerpc/powerpc.exp index a4c060a..7a49b1a 100644 --- a/ld/testsuite/ld-powerpc/powerpc.exp +++ b/ld/testsuite/ld-powerpc/powerpc.exp @@ -419,6 +419,7 @@ if [ supports_ppc64 ] then { run_dump_test "tlsld" run_dump_test "tlsie" run_dump_test "non-contiguous-powerpc64" + run_dump_test "tprel" } run_dump_test "localgot" @@ -459,3 +460,6 @@ run_dump_test "ppc476-shared" run_dump_test "ppc476-shared2" run_dump_test "non-contiguous-powerpc" + +run_dump_test "tprel32" +run_dump_test "tprelbad" diff --git a/ld/testsuite/ld-powerpc/tls32.d b/ld/testsuite/ld-powerpc/tls32.d index 664f9cd..e3e81f8 100644 --- a/ld/testsuite/ld-powerpc/tls32.d +++ b/ld/testsuite/ld-powerpc/tls32.d @@ -14,34 +14,34 @@ Disassembly of section \.text: .*: (7f c8 02 a6|a6 02 c8 7f) mflr r30 .*: (3f de 00 02|02 00 de 3f) addis r30,r30,2 .*: (3b de 80 a0|a0 80 de 3b) addi r30,r30,-32608 -.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0 -.*: (38 63 90 3c|3c 90 63 38) addi r3,r3,-28612 -.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0 -.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096 -.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0 -.*: (38 63 90 20|20 90 63 38) addi r3,r3,-28640 -.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0 -.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096 +.*: (60 00 00 00|00 00 00 60) nop +.*: (38 62 90 3c|3c 90 62 38) addi r3,r2,-28612 +.*: (60 00 00 00|00 00 00 60) nop +.*: (38 62 10 00|00 10 62 38) addi r3,r2,4096 +.*: (60 00 00 00|00 00 00 60) nop +.*: (38 62 90 20|20 90 62 38) addi r3,r2,-28640 +.*: (60 00 00 00|00 00 00 60) nop +.*: (38 62 10 00|00 10 62 38) addi r3,r2,4096 .*: (39 23 80 24|24 80 23 39) addi r9,r3,-32732 .*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0 .*: (81 49 80 28|28 80 49 81) lwz r10,-32728\(r9\) -.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0 -.*: (a1 49 90 30|30 90 49 a1) lhz r10,-28624\(r9\) +.*: (60 00 00 00|00 00 00 60) nop +.*: (a1 42 90 30|30 90 42 a1) lhz r10,-28624\(r2\) .*: (89 42 90 34|34 90 42 89) lbz r10,-28620\(r2\) -.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0 -.*: (99 49 90 38|38 90 49 99) stb r10,-28616\(r9\) -.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0 -.*: (38 63 90 00|00 90 63 38) addi r3,r3,-28672 -.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0 -.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096 +.*: (60 00 00 00|00 00 00 60) nop +.*: (99 42 90 38|38 90 42 99) stb r10,-28616\(r2\) +.*: (60 00 00 00|00 00 00 60) nop +.*: (38 62 90 00|00 90 62 38) addi r3,r2,-28672 +.*: (60 00 00 00|00 00 00 60) nop +.*: (38 62 10 00|00 10 62 38) addi r3,r2,4096 .*: (91 43 80 04|04 80 43 91) stw r10,-32764\(r3\) .*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0 .*: (91 49 80 08|08 80 49 91) stw r10,-32760\(r9\) -.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0 -.*: (b1 49 90 30|30 90 49 b1) sth r10,-28624\(r9\) +.*: (60 00 00 00|00 00 00 60) nop +.*: (b1 42 90 30|30 90 42 b1) sth r10,-28624\(r2\) .*: (a1 42 90 14|14 90 42 a1) lhz r10,-28652\(r2\) -.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0 -.*: (a9 49 90 18|18 90 49 a9) lha r10,-28648\(r9\) +.*: (60 00 00 00|00 00 00 60) nop +.*: (a9 42 90 18|18 90 42 a9) lha r10,-28648\(r2\) 0+1800120 <__tls_get_addr>: .*: (4e 80 00 20|20 00 80 4e) blr diff --git a/ld/testsuite/ld-powerpc/tlsexe32.d b/ld/testsuite/ld-powerpc/tlsexe32.d index b342093..d1a7c9c 100644 --- a/ld/testsuite/ld-powerpc/tlsexe32.d +++ b/ld/testsuite/ld-powerpc/tlsexe32.d @@ -17,30 +17,30 @@ Disassembly of section \.text: .*: (7c 63 12 14|14 12 63 7c) add r3,r3,r2 .*: (38 7f ff f8|f8 ff 7f 38) addi r3,r31,-8 .*: (48 00 00 65|65 00 00 48) bl .* <__tls_get_addr_opt@plt> -.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0 -.*: (38 63 90 1c|1c 90 63 38) addi r3,r3,-28644 -.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0 -.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096 +.*: (60 00 00 00|00 00 00 60) nop +.*: (38 62 90 1c|1c 90 62 38) addi r3,r2,-28644 +.*: (60 00 00 00|00 00 00 60) nop +.*: (38 62 10 00|00 10 62 38) addi r3,r2,4096 .*: (39 23 80 20|20 80 23 39) addi r9,r3,-32736 .*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0 .*: (81 49 80 24|24 80 49 81) lwz r10,-32732\(r9\) -.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0 -.*: (a1 49 90 2c|2c 90 49 a1) lhz r10,-28628\(r9\) +.*: (60 00 00 00|00 00 00 60) nop +.*: (a1 42 90 2c|2c 90 42 a1) lhz r10,-28628\(r2\) .*: (89 42 90 30|30 90 42 89) lbz r10,-28624\(r2\) -.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0 -.*: (99 49 90 34|34 90 49 99) stb r10,-28620\(r9\) -.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0 -.*: (38 63 90 00|00 90 63 38) addi r3,r3,-28672 -.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0 -.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096 +.*: (60 00 00 00|00 00 00 60) nop +.*: (99 42 90 34|34 90 42 99) stb r10,-28620\(r2\) +.*: (60 00 00 00|00 00 00 60) nop +.*: (38 62 90 00|00 90 62 38) addi r3,r2,-28672 +.*: (60 00 00 00|00 00 00 60) nop +.*: (38 62 10 00|00 10 62 38) addi r3,r2,4096 .*: (91 43 80 04|04 80 43 91) stw r10,-32764\(r3\) .*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0 .*: (91 49 80 08|08 80 49 91) stw r10,-32760\(r9\) -.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0 -.*: (b1 49 90 2c|2c 90 49 b1) sth r10,-28628\(r9\) +.*: (60 00 00 00|00 00 00 60) nop +.*: (b1 42 90 2c|2c 90 42 b1) sth r10,-28628\(r2\) .*: (a1 42 90 14|14 90 42 a1) lhz r10,-28652\(r2\) -.*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0 -.*: (a9 49 90 18|18 90 49 a9) lha r10,-28648\(r9\) +.*: (60 00 00 00|00 00 00 60) nop +.*: (a9 42 90 18|18 90 42 a9) lha r10,-28648\(r2\) .* <__tls_get_addr_opt@plt>: .*: (81 63 00 00|00 00 63 81) lwz r11,0\(r3\) diff --git a/ld/testsuite/ld-powerpc/tlsldopt32.d b/ld/testsuite/ld-powerpc/tlsldopt32.d index 5178fdb..228e7bc 100644 --- a/ld/testsuite/ld-powerpc/tlsldopt32.d +++ b/ld/testsuite/ld-powerpc/tlsldopt32.d @@ -10,32 +10,32 @@ Disassembly of section \.text: .*: .* nop -.* addis r29,r2,0 +.* nop .* mr r3,r29 -.* addi r3,r3,4096 +.* addi r3,r2,4096 .* addis r3,r3,0 .* lwz r3,-32768\(r3\) .* nop .* nop -.* addis r29,r2,0 +.* nop .* mr r3,r29 -.* addi r3,r3,4096 +.* addi r3,r2,4096 .* lwz r3,-32768\(r3\) .* nop .* nop .* nop .* nop .* nop -.* addis r29,r2,0 +.* nop .* mr r3,r29 -.* addi r3,r3,-28672 +.* addi r3,r2,-28672 .* lwz r3,0\(r3\) .* nop .* nop .* nop -.* addis r29,r2,0 +.* nop .* mr r3,r29 -.* addi r3,r3,-28672 +.* addi r3,r2,-28672 .* lwz r3,0\(r3\) .* nop .* nop diff --git a/ld/testsuite/ld-powerpc/tlsmark32.d b/ld/testsuite/ld-powerpc/tlsmark32.d index 3692755..448eda9 100644 --- a/ld/testsuite/ld-powerpc/tlsmark32.d +++ b/ld/testsuite/ld-powerpc/tlsmark32.d @@ -11,13 +11,13 @@ Disassembly of section \.text: 0+1800094 <_start>: .*: (48 00 00 14|14 00 00 48) b 18000a8 <_start\+0x14> -.*: (38 63 90 00|00 90 63 38) addi r3,r3,-28672 +.*: (38 62 90 00|00 90 62 38) addi r3,r2,-28672 .*: (80 83 00 00|00 00 83 80) lwz r4,0\(r3\) -.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0 +.*: (60 00 00 00|00 00 00 60) nop .*: (48 00 00 0c|0c 00 00 48) b 18000b0 <_start\+0x1c> -.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0 +.*: (60 00 00 00|00 00 00 60) nop .*: (4b ff ff ec|ec ff ff 4b) b 1800098 <_start\+0x4> -.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096 +.*: (38 62 10 00|00 10 62 38) addi r3,r2,4096 .*: (80 83 80 00|00 80 83 80) lwz r4,-32768\(r3\) 0+18000b8 <__tls_get_addr>: diff --git a/ld/testsuite/ld-powerpc/tlsopt4_32.d b/ld/testsuite/ld-powerpc/tlsopt4_32.d index 59c0a6a..32314b0 100644 --- a/ld/testsuite/ld-powerpc/tlsopt4_32.d +++ b/ld/testsuite/ld-powerpc/tlsopt4_32.d @@ -15,30 +15,30 @@ Disassembly of section \.text: Disassembly of section \.opt1: 0+1800098 <\.opt1>: -.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0 +.*: (60 00 00 00|00 00 00 60) nop .*: (2c 04 00 00|00 00 04 2c) cmpwi r4,0 .*: (41 82 00 0c|0c 00 82 41) beq .* -.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656 +.*: (38 62 90 10|10 90 62 38) addi r3,r2,-28656 .*: (48 00 00 08|08 00 00 48) b .* -.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656 +.*: (38 62 90 10|10 90 62 38) addi r3,r2,-28656 Disassembly of section \.opt2: 0+18000b0 <\.opt2>: -.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0 +.*: (60 00 00 00|00 00 00 60) nop .*: (2c 04 00 00|00 00 04 2c) cmpwi r4,0 .*: (41 82 00 08|08 00 82 41) beq .* -.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0 -.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656 +.*: (60 00 00 00|00 00 00 60) nop +.*: (38 62 90 10|10 90 62 38) addi r3,r2,-28656 Disassembly of section \.opt3: 0+18000c4 <\.opt3>: -.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0 +.*: (60 00 00 00|00 00 00 60) nop .*: (48 00 00 0c|0c 00 00 48) b .* -.*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0 +.*: (60 00 00 00|00 00 00 60) nop .*: (48 00 00 0c|0c 00 00 48) b .* -.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656 +.*: (38 62 90 10|10 90 62 38) addi r3,r2,-28656 .*: (48 00 00 08|08 00 00 48) b .* -.*: (38 63 90 08|08 90 63 38) addi r3,r3,-28664 +.*: (38 62 90 08|08 90 62 38) addi r3,r2,-28664 #pass diff --git a/ld/testsuite/ld-powerpc/tprel.d b/ld/testsuite/ld-powerpc/tprel.d new file mode 100644 index 0000000..f3135b0 --- /dev/null +++ b/ld/testsuite/ld-powerpc/tprel.d @@ -0,0 +1,12 @@ +#as: -a64 --defsym REG=13 +#ld: -melf64ppc +#objdump: -d + +.*: file format .* + +Disassembly of section \.text: + +.* <_start>: +.*: (60 00 00 00|00 00 00 60) nop +.*: (80 6d 90 00|00 90 6d 80) lwz r3,-28672\(r13\) +.*: (4e 80 00 20|20 00 80 4e) blr diff --git a/ld/testsuite/ld-powerpc/tprel.s b/ld/testsuite/ld-powerpc/tprel.s new file mode 100644 index 0000000..67a13e7 --- /dev/null +++ b/ld/testsuite/ld-powerpc/tprel.s @@ -0,0 +1,10 @@ + .section ".tbss","awT",@nobits + .p2align 2 +wot: .space 4 + + .text + .global _start +_start: + addis 3,REG,wot@tprel@ha + lwz 3,wot@tprel@l(3) + blr diff --git a/ld/testsuite/ld-powerpc/tprel32.d b/ld/testsuite/ld-powerpc/tprel32.d new file mode 100644 index 0000000..444db13 --- /dev/null +++ b/ld/testsuite/ld-powerpc/tprel32.d @@ -0,0 +1,13 @@ +#source: tprel.s +#as: -a32 --defsym REG=2 +#ld: -melf32ppc +#objdump: -d + +.*: file format .* + +Disassembly of section \.text: + +.* <_start>: +.*: (60 00 00 00|00 00 00 60) nop +.*: (80 62 90 00|00 90 62 80) lwz r3,-28672\(r2\) +.*: (4e 80 00 20|20 00 80 4e) blr diff --git a/ld/testsuite/ld-powerpc/tprelbad.d b/ld/testsuite/ld-powerpc/tprelbad.d new file mode 100644 index 0000000..c7fc60b --- /dev/null +++ b/ld/testsuite/ld-powerpc/tprelbad.d @@ -0,0 +1,12 @@ +#as: +#ld: +#objdump: -d + +.*: file format .* + +Disassembly of section \.text: + +.* <_start>: +.*: (3c 60 00 00|00 00 60 3c) lis r3,0 +.*: (38 63 90 00|00 90 63 38) addi r3,r3,-28672 +.*: (4e 80 00 20|20 00 80 4e) blr diff --git a/ld/testsuite/ld-powerpc/tprelbad.s b/ld/testsuite/ld-powerpc/tprelbad.s new file mode 100644 index 0000000..1b9a117 --- /dev/null +++ b/ld/testsuite/ld-powerpc/tprelbad.s @@ -0,0 +1,10 @@ + .section ".tbss","awT",@nobits + .p2align 2 +wot: .space 4 + + .text + .global _start +_start: + lis 3,wot@tprel@ha + addi 3,3,wot@tprel@l + blr -- cgit v1.1