From ee804238f097e91088a340c15891170f2748b4fd Mon Sep 17 00:00:00 2001 From: Jiong Wang Date: Wed, 3 Sep 2014 14:40:41 +0100 Subject: [PATCH/AArch64] Implement LSE feature 2014-09-03 Jiong Wang gas/ * config/tc-aarch64.c (parse_operands): Recognize PAIRREG. (aarch64_features): Add entry for lse extension. include/opcode/ * aarch64.h (AARCH64_FEATURE_LSE): New feature added. (aarch64_opnd): Add AARCH64_OPND_PAIRREG. (aarch64_insn_class): Add lse_atomic. (F_LSE_SZ): New field added. (opcode_has_special_coder): Recognize F_LSE_SZ. opcode/ * aarch64-tbl.h (QL_R4NIL): New qualifiers. (aarch64_feature_lse): New feature added. (LSE): New Added. (aarch64_opcode_table): New LSE instructions added. Improve descriptions for ldarb/ldarh/ldar. (aarch64_opcode_table): Describe PAIRREG. * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz. * aarch64-opc.c (fields): Add entry for F_LSE_SZ. (aarch64_print_operand): Recognize PAIRREG. (operand_general_constraint_met_p): Check reg pair constraints for CASP instructions. * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg. (do_special_decoding): Recognize F_LSE_SZ. * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ. gas/testsuite/ * gas/aarch64/lse-atomic.d: New. * gas/aarch64/lse-atomic.s: Likewise. * gas/aarch64/illegal-lse.d: Likewise. * gas/aarch64/illegal-lse.l: Likewise. * gas/aarch64/illegal-lse.s: Likewise. * gas/aarch64/diagnostic.s: Check processor feature detect for lse instruction. * gas/aarch64/diagnostic.l: Likewise. --- include/opcode/ChangeLog | 8 ++++++++ include/opcode/aarch64.h | 9 +++++++-- 2 files changed, 15 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 955706c..58d9f99 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,11 @@ +2014-09-03 Jiong Wang + + * aarch64.h (AARCH64_FEATURE_LSE): New feature added. + (aarch64_opnd): Add AARCH64_OPND_PAIRREG. + (aarch64_insn_class): Add lse_atomic. + (F_LSE_SZ): New field added. + (opcode_has_special_coder): Recognize F_LSE_SZ. + 2014-08-26 Maciej W. Rozycki * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B' diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index c6d6fc5..c0afd74 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -38,6 +38,7 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ +#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */ /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ @@ -106,6 +107,7 @@ enum aarch64_opnd AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ + AARCH64_OPND_PAIRREG, /* Paired register operand. */ AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ @@ -340,6 +342,7 @@ enum aarch64_insn_class loadlit, log_imm, log_shift, + lse_atomic, movewide, pcreladdr, ic_system, @@ -550,7 +553,9 @@ extern aarch64_opcode aarch64_opcode_table[]; #define F_N (1 << 23) /* Opcode dependent field. */ #define F_OD(X) (((X) & 0x7) << 24) -/* Next bit is 27. */ +/* Instruction has the field of 'sz'. */ +#define F_LSE_SZ (1 << 27) +/* Next bit is 28. */ static inline bfd_boolean alias_opcode_p (const aarch64_opcode *opcode) @@ -599,7 +604,7 @@ get_opcode_dependent_value (const aarch64_opcode *opcode) static inline bfd_boolean opcode_has_special_coder (const aarch64_opcode *opcode) { - return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T + return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE : FALSE; } -- cgit v1.1