From c7927a3c0ef1d97faf24f1df31baf419e2d92fa1 Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Tue, 29 Sep 2009 14:17:19 +0000 Subject: bfd * Makefile.am (ALL_MACHINES): Add cpu-rx.lo. (ALL_MACHINES_CFILES): Add cpu-rx.c. (BFD32_BACKENDS): Add elf32-rx.lo. (BFD32_BACKENDS_CFILES): Add elf32-rx.c. * archures.c (bfd_architecture): Add bfd_arch_rx and bfd_mach_rx. Export bfd_rx_arch. (bfd_archures_list): Add bfd_rx_arch. * config.bfd: Add entry for rx-*-elf. * configure.in: Add entries for bfd_elf32_rx_le_vec and bfd_elf32_rx_be_vec. * reloc.c: Add RX relocations. * targets.c: Add RX target vectors. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. * cpu-rx.c: New file. * elf32-rx.c: New file. binutils * readelf.c: Add support for RX target. * MAINTAINERS: Add DJ and NickC as maintainers for RX. gas * Makefile.am: Add RX target. * configure.in: Likewise. * configure.tgt: Likewise. * read.c (do_repeat_with_expander): New function. * read.h: Provide a prototype for do_repeat_with_expander. * doc/Makefile.am: Add RX target documentation. * doc/all.texi: Likewise. * doc/as.texinfo: Likewise. * Makefile.in: Regenerate. * NEWS: Mention support for RX architecture. * configure: Regenerate. * doc/Makefile.in: Regenerate. * config/rx-defs.h: New file. * config/rx-parse.y: New file. * config/tc-rx.h: New file. * config/tc-rx.c: New file. * doc/c-rx.texi: New file. gas/testsuite * gas/rx: New directory. * gas/rx/*: New set of test cases. * gas/elf/section2.e-rx: New expected output file. * gas/all/gas.exp: Add support for RX target. * gas/elf/elf.exp: Likewise. * gas/lns/lns.exp: Likewise. * gas/macros/macros.exp: Likewise. include * dis-asm.h: Add prototype for print_insn_rx. include/elf * rx.h: New file. include/opcode * rx.h: New file. ld * Makefile.am: Add rules to build RX emulation. * configure.tgt: Likewise. * NEWS: Mention support for RX architecture. * Makefile.in: Regenerate. * emulparams/elf32rx.sh: New file. * emultempl/rxelf.em: New file. opcodes * Makefile.am: Add RX files. * configure.in: Add support for RX target. * disassemble.c: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * opc2c.c: New file. * rx-decode.c: New file. * rx-decode.opc: New file. * rx-dis.c: New file. --- include/ChangeLog | 4 + include/dis-asm.h | 1 + include/elf/ChangeLog | 4 + include/elf/rx.h | 134 +++++++++++++++++++++++++++++ include/opcode/ChangeLog | 4 + include/opcode/rx.h | 218 +++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 365 insertions(+) create mode 100644 include/elf/rx.h create mode 100644 include/opcode/rx.h (limited to 'include') diff --git a/include/ChangeLog b/include/ChangeLog index db95d46..7e8f345 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2009-09-29 DJ Delorie + + * dis-asm.h: Add prototype for print_insn_rx. + 2009-09-25 Dodji Seketeli * dwarf2.h (enum dwarf_tag): Rename DW_TAG_template_parameter_pack and diff --git a/include/dis-asm.h b/include/dis-asm.h index 47236a0..3d126be 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -296,6 +296,7 @@ extern int print_insn_xtensa (bfd_vma, disassemble_info *); extern int print_insn_z80 (bfd_vma, disassemble_info *); extern int print_insn_z8001 (bfd_vma, disassemble_info *); extern int print_insn_z8002 (bfd_vma, disassemble_info *); +extern int print_insn_rx (bfd_vma, disassemble_info *); extern disassembler_ftype arc_get_disassembler (void *); extern disassembler_ftype cris_get_disassembler (bfd *); diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index a33fb84..3841f35 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,7 @@ +2009-09-29 DJ Delorie + + * rx.h: New file. + 2009-09-21 Alan Modra * ppc.h (DT_PPC_TLSOPT): Define. diff --git a/include/elf/rx.h b/include/elf/rx.h new file mode 100644 index 0000000..1e04f3f --- /dev/null +++ b/include/elf/rx.h @@ -0,0 +1,134 @@ +/* RX ELF support for BFD. + Copyright (C) 2008, 2009 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_RX_H +#define _ELF_RX_H + +#include "elf/reloc-macros.h" + +/* Note that there are a few internal relocation types used by the + linker to do link-time relaxation. If you update this file, please + check elf32-rx.c to see if any of the internal relocations need to + be, er, relocated. */ + +/* Preliminary relocations. */ +START_RELOC_NUMBERS (elf_rx_reloc_type) + + RELOC_NUMBER (R_RX_NONE, 0x00) + /* These are for data, and are bi-endian. */ + RELOC_NUMBER (R_RX_DIR32, 0x01) /* Was: R_RX_32. */ + RELOC_NUMBER (R_RX_DIR24S, 0x02) /* Was: R_RX_24. */ + RELOC_NUMBER (R_RX_DIR16, 0x03) + RELOC_NUMBER (R_RX_DIR16U, 0x04) /* Was: R_RX_16_UNS. */ + RELOC_NUMBER (R_RX_DIR16S, 0x05) /* Was: R_RX_16. */ + RELOC_NUMBER (R_RX_DIR8, 0x06) + RELOC_NUMBER (R_RX_DIR8U, 0x07) /* Was: R_RX_8_UNS. */ + RELOC_NUMBER (R_RX_DIR8S, 0x08) /* Was: R_RX_8. */ + + /* Signed pc-relative values. */ + RELOC_NUMBER (R_RX_DIR24S_PCREL, 0x09) /* Was: R_RX_24_PCREL. */ + RELOC_NUMBER (R_RX_DIR16S_PCREL, 0x0a) /* Was: R_RX_16_PCREL. */ + RELOC_NUMBER (R_RX_DIR8S_PCREL, 0x0b) /* Was: R_RX_8_PCREL. */ + + /* These are for fields in the instructions. */ + RELOC_NUMBER (R_RX_DIR16UL, 0x0c) + RELOC_NUMBER (R_RX_DIR16UW, 0x0d) + RELOC_NUMBER (R_RX_DIR8UL, 0x0e) + RELOC_NUMBER (R_RX_DIR8UW, 0x0f) + RELOC_NUMBER (R_RX_DIR32_REV, 0x10) + RELOC_NUMBER (R_RX_DIR16_REV, 0x11) + RELOC_NUMBER (R_RX_DIR3U_PCREL, 0x12) + + /* These are extensions added by Red Hat. */ + RELOC_NUMBER (R_RX_RH_3_PCREL, 0x20) /* Like R_RX_DIR8S_PCREL but only 3-bits. */ + RELOC_NUMBER (R_RX_RH_16_OP, 0x21) /* Like R_RX_DIR16 but for opcodes - always big endian. */ + RELOC_NUMBER (R_RX_RH_24_OP, 0x22) /* Like R_RX_DIR24S but for opcodes - always big endian. */ + RELOC_NUMBER (R_RX_RH_32_OP, 0x23) /* Like R_RX_DIR32 but for opcodes - always big endian. */ + RELOC_NUMBER (R_RX_RH_24_UNS, 0x24) /* Like R_RX_DIR24S but for unsigned values. */ + RELOC_NUMBER (R_RX_RH_8_NEG, 0x25) /* Like R_RX_DIR8 but -x is stored. */ + RELOC_NUMBER (R_RX_RH_16_NEG, 0x26) /* Like R_RX_DIR16 but -x is stored. */ + RELOC_NUMBER (R_RX_RH_24_NEG, 0x27) /* Like R_RX_DIR24S but -x is stored. */ + RELOC_NUMBER (R_RX_RH_32_NEG, 0x28) /* Like R_RX_DIR32 but -x is stored. */ + RELOC_NUMBER (R_RX_RH_DIFF, 0x29) /* Subtract from a previous relocation. */ + RELOC_NUMBER (R_RX_RH_GPRELB, 0x2a) /* Byte value, relative to __gp. */ + RELOC_NUMBER (R_RX_RH_GPRELW, 0x2b) /* Word value, relative to __gp. */ + RELOC_NUMBER (R_RX_RH_GPRELL, 0x2c) /* Long value, relative to __gp. */ + RELOC_NUMBER (R_RX_RH_RELAX, 0x2d) /* Marks opcodes suitable for linker relaxation. */ + + /* These are for complex relocs. */ + RELOC_NUMBER (R_RX_ABS32, 0x41) + RELOC_NUMBER (R_RX_ABS24S, 0x42) + RELOC_NUMBER (R_RX_ABS16, 0x43) + RELOC_NUMBER (R_RX_ABS16U, 0x44) + RELOC_NUMBER (R_RX_ABS16S, 0x45) + RELOC_NUMBER (R_RX_ABS8, 0x46) + RELOC_NUMBER (R_RX_ABS8U, 0x47) + RELOC_NUMBER (R_RX_ABS8S, 0x48) + RELOC_NUMBER (R_RX_ABS24S_PCREL, 0x49) + RELOC_NUMBER (R_RX_ABS16S_PCREL, 0x4a) + RELOC_NUMBER (R_RX_ABS8S_PCREL, 0x4b) + RELOC_NUMBER (R_RX_ABS16UL, 0x4c) + RELOC_NUMBER (R_RX_ABS16UW, 0x4d) + RELOC_NUMBER (R_RX_ABS8UL, 0x4e) + RELOC_NUMBER (R_RX_ABS8UW, 0x4f) + RELOC_NUMBER (R_RX_ABS32_REV, 0x50) + RELOC_NUMBER (R_RX_ABS16_REV, 0x51) + + RELOC_NUMBER (R_RX_SYM, 0x80) + RELOC_NUMBER (R_RX_OPneg, 0x81) + RELOC_NUMBER (R_RX_OPadd, 0x82) + RELOC_NUMBER (R_RX_OPsub, 0x83) + RELOC_NUMBER (R_RX_OPmul, 0x84) + RELOC_NUMBER (R_RX_OPdiv, 0x85) + RELOC_NUMBER (R_RX_OPshla, 0x86) + RELOC_NUMBER (R_RX_OPshra, 0x87) + RELOC_NUMBER (R_RX_OPsctsize, 0x88) + RELOC_NUMBER (R_RX_OPscttop, 0x8d) + RELOC_NUMBER (R_RX_OPand, 0x90) + RELOC_NUMBER (R_RX_OPor, 0x91) + RELOC_NUMBER (R_RX_OPxor, 0x92) + RELOC_NUMBER (R_RX_OPnot, 0x93) + RELOC_NUMBER (R_RX_OPmod, 0x94) + RELOC_NUMBER (R_RX_OPromtop, 0x95) + RELOC_NUMBER (R_RX_OPramtop, 0x96) + +END_RELOC_NUMBERS (R_RX_max) + +#define EF_RX_CPU_RX 0x00000079 /* FIXME: correct value? */ +#define EF_RX_CPU_MASK 0x0000007F /* specific cpu bits. */ +#define EF_RX_ALL_FLAGS (EF_RX_CPU_MASK) + +/* Values for the e_flags field in the ELF header. */ +#define E_FLAG_RX_64BIT_DOUBLES (1 << 0) +#define E_FLAG_RX_DSP (1 << 1) /* Defined in the RX CPU Object file specification, but not explained. */ + +/* These define the addend field of R_RX_RH_RELAX relocations. */ +#define RX_RELAXA_IMM6 0x00000010 /* Imm8/16/24/32 at bit offset 6. */ +#define RX_RELAXA_IMM12 0x00000020 /* Imm8/16/24/32 at bit offset 12. */ +#define RX_RELAXA_DSP4 0x00000040 /* Dsp0/8/16 at bit offset 4. */ +#define RX_RELAXA_DSP6 0x00000080 /* Dsp0/8/16 at bit offset 6. */ +#define RX_RELAXA_DSP14 0x00000100 /* Dsp0/8/16 at bit offset 14. */ +#define RX_RELAXA_BRA 0x00000200 /* Any type of branch (must be decoded). */ +#define RX_RELAXA_RNUM 0x0000000f /* Number of associated relocations. */ +/* These mark the place where alignment is requested, and the place where the filler bytes end. */ +#define RX_RELAXA_ALIGN 0x10000000 /* Start alignment; the remaining bits are the alignment value. */ +#define RX_RELAXA_ELIGN 0x20000000 /* End alignment; the remaining bits are the alignment value. */ +#define RX_RELAXA_ANUM 0x00ffffff /* Alignment amount, in bytes (i.e. .balign). */ + +#endif /* _ELF_RX_H */ diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 29f717b..2fddcdf 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2009-09-29 DJ Delorie + + * rx.h: New file. + 2009-09-22 Peter Bergner * ppc.h (ppc_cpu_t): Typedef to uint64_t. diff --git a/include/opcode/rx.h b/include/opcode/rx.h new file mode 100644 index 0000000..7081ccc --- /dev/null +++ b/include/opcode/rx.h @@ -0,0 +1,218 @@ +/* Opcode decoder for the Renesas RX + Copyright 2008, 2009 + Free Software Foundation, Inc. + Written by DJ Delorie + + This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +/* The RX decoder in libopcodes is used by the simulator, gdb's + analyzer, and the disassembler. Given an opcode data source, + it decodes the next opcode into the following structures. */ + +typedef enum +{ + RX_AnySize = 0, + RX_Byte, /* undefined extension */ + RX_UByte, + RX_SByte, + RX_Word, /* undefined extension */ + RX_UWord, + RX_SWord, + RX_3Byte, + RX_Long, +} RX_Size; + +typedef enum +{ + RX_Operand_None, + RX_Operand_Immediate, /* #addend */ + RX_Operand_Register, /* Rn */ + RX_Operand_Indirect, /* [Rn + addend] */ + RX_Operand_Postinc, /* [Rn+] */ + RX_Operand_Predec, /* [-Rn] */ + RX_Operand_Condition, /* eq, gtu, etc */ + RX_Operand_Flag, /* [UIOSZC] */ +} RX_Operand_Type; + +typedef enum +{ + RXO_unknown, + RXO_mov, /* d = s (signed) */ + RXO_movbi, /* d = [s,s2] (signed) */ + RXO_movbir, /* [s,s2] = d (signed) */ + RXO_pushm, /* s..s2 */ + RXO_popm, /* s..s2 */ + RXO_pusha, /* &s */ + RXO_xchg, /* s <-> d */ + RXO_stcc, /* d = s if cond(s2) */ + RXO_rtsd, /* rtsd, 1=imm, 2-0 = reg if reg type */ + + /* These are all either d OP= s or, if s2 is set, d = s OP s2. Note + that d may be "None". */ + RXO_and, + RXO_or, + RXO_xor, + RXO_add, + RXO_sub, + RXO_mul, + RXO_div, + RXO_divu, + RXO_shll, + RXO_shar, + RXO_shlr, + + RXO_adc, /* d = d + s + carry */ + RXO_sbb, /* d = d - s - ~carry */ + RXO_abs, /* d = |s| */ + RXO_max, /* d = max(d,s) */ + RXO_min, /* d = min(d,s) */ + RXO_emul, /* d:64 = d:32 * s */ + RXO_emulu, /* d:64 = d:32 * s (unsigned) */ + RXO_ediv, /* d:64 / s; d = quot, d+1 = rem */ + RXO_edivu, /* d:64 / s; d = quot, d+1 = rem */ + + RXO_rolc, /* d <<= 1 through carry */ + RXO_rorc, /* d >>= 1 through carry*/ + RXO_rotl, /* d <<= #s without carry */ + RXO_rotr, /* d >>= #s without carry*/ + RXO_revw, /* d = revw(s) */ + RXO_revl, /* d = revl(s) */ + RXO_branch, /* pc = d if cond(s) */ + RXO_branchrel,/* pc += d if cond(s) */ + RXO_jsr, /* pc = d */ + RXO_jsrrel, /* pc += d */ + RXO_rts, + RXO_nop, + + RXO_scmpu, + RXO_smovu, + RXO_smovb, + RXO_suntil, + RXO_swhile, + RXO_smovf, + RXO_sstr, + + RXO_rmpa, + RXO_mulhi, + RXO_mullo, + RXO_machi, + RXO_maclo, + RXO_mvtachi, + RXO_mvtaclo, + RXO_mvfachi, + RXO_mvfacmi, + RXO_mvfaclo, + RXO_racw, + + RXO_sat, /* sat(d) */ + RXO_satr, + + RXO_fadd, /* d op= s */ + RXO_fcmp, + RXO_fsub, + RXO_ftoi, + RXO_fmul, + RXO_fdiv, + RXO_round, + RXO_itof, + + RXO_bset, /* d |= (1< = cond(s2) */ + + RXO_clrpsw, /* flag index in d */ + RXO_setpsw, /* flag index in d */ + + RXO_mvtcp, /* cop# in s2, cop[d] = s */ + RXO_mvfcp, /* cop# in s2, d = cop[s] */ + RXO_opecp, /* cop# in s2, do cop[s] */ + + RXO_rtfi, + RXO_rte, + RXO_rtd, /* undocumented */ + RXO_brk, + RXO_dbt, /* undocumented */ + RXO_int, /* vector id in s */ + RXO_stop, + RXO_wait, + + RXO_sccnd, /* d = cond(s) ? 1 : 0 */ +} RX_Opcode_ID; + +/* Condition bitpatterns, as registers. */ +#define RXC_eq 0 +#define RXC_z 0 +#define RXC_ne 1 +#define RXC_nz 1 +#define RXC_c 2 +#define RXC_nc 3 +#define RXC_gtu 4 +#define RXC_leu 5 +#define RXC_pz 6 +#define RXC_n 7 +#define RXC_ge 8 +#define RXC_lt 9 +#define RXC_gt 10 +#define RXC_le 11 +#define RXC_o 12 +#define RXC_no 13 +#define RXC_always 14 +#define RXC_never 15 + +typedef struct +{ + RX_Operand_Type type; + int reg; + int addend; + RX_Size size; +} RX_Opcode_Operand; + +typedef struct +{ + RX_Opcode_ID id; + int n_bytes; + int prefix; + char * syntax; + RX_Size size; + /* By convention, these are destination, source1, source2. */ + RX_Opcode_Operand op[3]; + + /* The logic here is: + newflags = (oldflags & ~(int)flags_0) | flags_1 | (op_flags & flags_s) + Only the O, S, Z, and C flags are affected. */ + char flags_0; /* This also clears out flags-to-be-set. */ + char flags_1; + char flags_s; +} RX_Opcode_Decoded; + +/* Within the syntax, %c-style format specifiers are as follows: + + %% = '%' character + %0 = operand[0] (destination) + %1 = operand[1] (source) + %2 = operand[2] (2nd source) + %s = operation size (b/w/l) + %SN = operand size [N] (N=0,1,2) + %aN = op[N] as an address (N=0,1,2) + + Register numbers 0..15 are general registers. 16..31 are control + registers. 32..47 are condition codes. */ + +int rx_decode_opcode (unsigned long, RX_Opcode_Decoded *, int (*)(void *), void *); -- cgit v1.1