From bdd582dbf14f12998a0003b5aa772d7868bc3dc7 Mon Sep 17 00:00:00 2001 From: Graham Markall Date: Tue, 21 Jun 2016 14:03:08 +0100 Subject: Arc assembler: Convert nps400 from a machine type to an extension. gas * config/tc-arc.c (check_cpu_feature, md_parse_option): Add nps400 option and feature. Add check for nps400 feature. Refactor existing checks to check subclass before feature enablement. (md_show_usage): Document flags for NPS-400 and add some other undocumented flags. (cpu_type): Remove nps400 CPU type entry (check_zol): Remove bfd_mach_arc_nps400 case. (md_show_usage): Add help on -mcpu=nps400. (cpu_types): Add entry for nps400 as arc700 plus nps400 extension set. * doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and -fpuda flags. Document -mcpu=nps400. * testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change expected flags to match ARC700 instead of NPS400. * testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400. * testsuite/gas/arc/nps-400-2.d: Likewise. * testsuite/gas/arc/nps-400-3.d: Likewise. * testsuite/gas/arc/nps-400-4.d: Likewise. * testsuite/gas/arc/nps-400-5.d: Likewise. * testsuite/gas/arc/nps-400-6.d: Likewise. * testsuite/gas/arc/nps-400-7.d: Likewise. * testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to avoid clash with cbba instruction. * testsuite/gas/arc/textinsn2op01.d: Likewise. * testsuite/gas/arc/textinsn3op.d: Likewise. * testsuite/gas/arc/textinsn3op.s: Likewise. * testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using -mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags. binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400 case. ld * testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400. * testsuite/ld-arc/nps-1b.d: Likewise. include * opcode/arc.h: Add nps400 extension and instruction subclass. Remove ARC_OPCODE_NPS400 * elf/arc.h: Remove E_ARC_MACH_NPS400 opcodes * arc-dis.c (arc_insn_length): Add comment on instruction length. Use same method for determining instruction length on ARC700 and NPS-400. (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400. * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions with the NPS400 subclass. * arc-opc.c: Likewise. bfd * archures.c: Remove bfd_mach_arc_nps400. * bfd-in2.h: Likewise. * cpu-arc.c (arch_info_struct): Likewise. * elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing): Likewise. --- include/ChangeLog | 7 +++++++ include/elf/arc.h | 1 - include/opcode/arc.h | 3 ++- 3 files changed, 9 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/ChangeLog b/include/ChangeLog index cb9dacc..a9f380f 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,10 @@ +2016-06-21 Graham Markall + + * opcode/arc.h: Add nps400 extension and instruction + subclass. + Remove ARC_OPCODE_NPS400 + * elf/arc.h: Remove E_ARC_MACH_NPS400 + 2016-06-17 Jose E. Marchesi * opcode/sparc.h (enum sparc_opcode_arch_val): Add diff --git a/include/elf/arc.h b/include/elf/arc.h index 2aed25d..47381f3 100644 --- a/include/elf/arc.h +++ b/include/elf/arc.h @@ -48,7 +48,6 @@ END_RELOC_NUMBERS (R_ARC_max) #define E_ARC_MACH_ARC600 0x00000002 #define E_ARC_MACH_ARC601 0x00000004 #define E_ARC_MACH_ARC700 0x00000003 -#define E_ARC_MACH_NPS400 0x00000007 #define EF_ARC_CPU_ARCV2EM 0x00000005 #define EF_ARC_CPU_ARCV2HS 0x00000006 diff --git a/include/opcode/arc.h b/include/opcode/arc.h index adbae74..f8f1955 100644 --- a/include/opcode/arc.h +++ b/include/opcode/arc.h @@ -70,6 +70,7 @@ typedef enum MPY7E, MPY8E, MPY9E, + NPS400, QUARKSE, SHFT1, SHFT2, @@ -172,7 +173,6 @@ extern const struct arc_opcode arc_opcodes[]; #define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */ #define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */ #define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */ -#define ARC_OPCODE_NPS400 0x0010 /* NPS400 specific insns. */ /* CPU combi. */ #define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \ @@ -186,6 +186,7 @@ extern const struct arc_opcode arc_opcodes[]; #define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */ #define ARC_MPY 0x0004 #define ARC_MULT 0x0004 +#define ARC_NPS400 0x0008 /* Floating point support. */ #define ARC_DPFP 0x0010 -- cgit v1.1