From 8cf50cb070642d73acc537010d71c912f921861c Mon Sep 17 00:00:00 2001 From: Jiong Wang Date: Wed, 4 Jan 2017 14:27:52 +0000 Subject: [DWARF] Sync GCC dwarf.def change on AArch64 include/ * dwarf2.def: Sync with mainline gcc sources. --- include/ChangeLog | 10 ++++++++++ include/dwarf2.def | 9 ++++++++- 2 files changed, 18 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/ChangeLog b/include/ChangeLog index a518342..f0569be 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,13 @@ +2017-01-04 Jiong Wang + + * dwarf2.def: Sync with mainline gcc sources. + + 2017-01-04 Richard Earnshaw + Jiong Wang + + * dwarf2.def (DW_OP_AARCH64_operation): Reserve the number 0xea. + (DW_CFA_GNU_window_save): Comments the multiplexing on AArch64. + 2017-01-04 Szabolcs Nagy * opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define. diff --git a/include/dwarf2.def b/include/dwarf2.def index 4596c9a..ddadacc 100644 --- a/include/dwarf2.def +++ b/include/dwarf2.def @@ -685,6 +685,12 @@ DW_OP (DW_OP_HP_unmod_range, 0xe5) DW_OP (DW_OP_HP_tls, 0xe6) /* PGI (STMicroelectronics) extensions. */ DW_OP (DW_OP_PGI_omp_thread_num, 0xf8) +/* AARCH64 extensions. + DW_OP_AARCH64_operation takes one mandatory unsigned LEB128 operand. + Bits[6:0] of this operand is the action code, all others bits are initialized + to 0 except explicitly documented for one action. Please refer AArch64 DWARF + ABI documentation for details. */ +DW_OP (DW_OP_AARCH64_operation, 0xea) DW_END_OP DW_FIRST_ATE (DW_ATE_void, 0x0) @@ -766,7 +772,8 @@ DW_CFA (DW_CFA_hi_user, 0x3f) /* SGI/MIPS specific. */ DW_CFA (DW_CFA_MIPS_advance_loc8, 0x1d) -/* GNU extensions. */ +/* GNU extensions. + NOTE: DW_CFA_GNU_window_save is multiplexed on Sparc and AArch64. */ DW_CFA (DW_CFA_GNU_window_save, 0x2d) DW_CFA (DW_CFA_GNU_args_size, 0x2e) DW_CFA (DW_CFA_GNU_negative_offset_extended, 0x2f) -- cgit v1.1