From 8b082fb134d844804676e8a0f5ab08738952793c Mon Sep 17 00:00:00 2001 From: Thiemo Seufer Date: Tue, 20 Feb 2007 13:28:56 +0000 Subject: [ gas/ChangeLog ] * config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2, ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support. (macro_build): Add case '2'. (macro): Expand M_BALIGN to nop, packrl.ph or balign. (validate_mips_insn): Add support for balign instruction. (mips_ip): Handle DSP R2 instructions. Support balign instruction. (OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE, md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2 command line options. (s_mipsset): Add support for .set dspr2 and .set nodspr2 directives. (md_show_usage): Add -mdspr2 and -mno-dspr2 help output. * doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2, .set dspr2, .set nodspr2. [ gas/testsuite/ChangeLog ] * gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for DSP R2. * gas/mips/mips.exp: Run new test. [ include/opcode/Changelog ] * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. (INSN_DSPR2): Add flag for DSP R2 instructions. (M_BALIGN): New macro. [ opcodes/ChangeLog ] * mips-dis.c (mips_arch_choices): Add DSP R2 support. (print_insn_args): Add support for balign instruction. * mips-opc.c (D33): New shortcut for DSP R2 instructions. (mips_builtin_opcodes): Add DSP R2 instructions. [ sim/mips/ChangeLog ] * Makefile.in (IGEN_INCLUDE): Add dsp2.igen. * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add dsp2 to sim_igen_machine. * configure: Regenerate. * dsp.igen (do_ph_op): Add MUL support when op = 2. (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph. (mulq_rs.ph): Use do_ph_mulq. (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen. * mips.igen: Add dsp2 model and include dsp2.igen. (MFHI, MFLO, MTHI, MTLO): Extend these instructions for for *mips32r2, *mips64r2, *dsp. (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions for *mips32r2, *mips64r2, *dsp2. * dsp2.igen: New file for MIPS DSP REV 2 ASE. [ sim/testsuite/sim/mips/ChangeLog ] * basic.exp: Run the dsp2 test. * utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro. * mips32-dsp2.s: New test. --- include/opcode/ChangeLog | 7 +++++++ include/opcode/mips.h | 12 +++++++++--- 2 files changed, 16 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index f037b73..b1c26a4 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,10 @@ +2007-02-20 Thiemo Seufer + Chao-Ying Fu + + * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. + (INSN_DSPR2): Add flag for DSP R2 instructions. + (M_BALIGN): New macro. + 2007-02-14 Alan Modra * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm diff --git a/include/opcode/mips.h b/include/opcode/mips.h index dd99c4d..71822a4 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -169,6 +169,8 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US #define OP_MASK_WRDSP 0x3f #define OP_SH_RDDSP 16 #define OP_MASK_RDDSP 0x3f +#define OP_SH_BP 11 +#define OP_MASK_BP 0x3 /* MIPS MT ASE */ #define OP_SH_MT_U 5 @@ -340,6 +342,7 @@ struct mips_opcode "Z" MDMX source register (OP_*_FT) DSP ASE usage: + "2" 2 bit unsigned immediate for byte align (OP_*_BP) "3" 3 bit unsigned immediate (OP_*_SA3) "4" 4 bit unsigned immediate (OP_*_SA4) "5" 8 bit unsigned immediate (OP_*_IMM8) @@ -374,7 +377,7 @@ struct mips_opcode "+" Start of extension sequence. Characters used so far, for quick reference when adding more: - "34567890" + "234567890" "%[]<>(),+:'@!$*&" "ABCDEFGHIJKLMNOPQRSTUVWXYZ" "abcdefghijklopqrstuvwxz" @@ -485,7 +488,7 @@ struct mips_opcode #define INSN_ISA64R2 0x00000100 /* Masks used for MIPS-defined ASEs. */ -#define INSN_ASE_MASK 0x1c00f000 +#define INSN_ASE_MASK 0x3c00f000 /* DSP ASE */ #define INSN_DSP 0x00001000 @@ -522,8 +525,10 @@ struct mips_opcode #define INSN_MDMX 0x04000000 /* MT ASE */ #define INSN_MT 0x08000000 -/* SmartMIPS ASE. */ +/* SmartMIPS ASE */ #define INSN_SMARTMIPS 0x10000000 +/* DSP R2 ASE */ +#define INSN_DSPR2 0x20000000 /* MIPS ISA defines, use instead of hardcoding ISA level. */ @@ -608,6 +613,7 @@ enum M_ADD_I, M_ADDU_I, M_AND_I, + M_BALIGN, M_BEQ, M_BEQ_I, M_BEQL_I, -- cgit v1.1