From 4211a3400108b45732415cda0cacb087ab8690b1 Mon Sep 17 00:00:00 2001 From: Cooper Qu Date: Wed, 2 Sep 2020 14:06:03 +0800 Subject: CSKY: Add CPU CK803r3. Move divul and divsl to CSKYV2_ISA_3E3R3 instruction set, which is enabled by ck803r3, and it's still a part of enhance DSP instruction set. gas/ * config/tc-csky.c (csky_cpus): Add ck803r3. (CSKY_ISA_803R3): Define. (CSKY_ISA_803R2): Refine, use CSKY_ISA_803R1. include/ * opcode/csky.h (CSKYV2_ISA_3E3R3): Define. opcodes/ * csky-opc.h (csky_v2_opcodes): Move divul and divsl to CSKYV2_ISA_3E3R3 instruction set. --- include/ChangeLog | 4 ++++ include/opcode/csky.h | 1 + 2 files changed, 5 insertions(+) (limited to 'include') diff --git a/include/ChangeLog b/include/ChangeLog index 9daa866..c6f00b3 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2020-09-02 Cooper Qu + + * opcode/csky.h (CSKYV2_ISA_3E3R3): Define. + 2020-08-31 Alan Modra PR 26493 diff --git a/include/opcode/csky.h b/include/opcode/csky.h index 493e822..ab2b210 100644 --- a/include/opcode/csky.h +++ b/include/opcode/csky.h @@ -31,6 +31,7 @@ #define CSKYV2_ISA_3E3R1 (1L << 6) #define CSKYV2_ISA_3E3R2 (1L << 7) #define CSKYV2_ISA_10E60 (1L << 8) +#define CSKYV2_ISA_3E3R3 (1L << 9) #define CSKY_ISA_TRUST (1L << 11) #define CSKY_ISA_CACHE (1L << 12) -- cgit v1.1