From fd1dc4a0c1b87c1efa7e0398fd47fd1e87fa0fb4 Mon Sep 17 00:00:00 2001 From: Matthew Malcomson Date: Thu, 9 May 2019 10:29:26 +0100 Subject: [binutils][aarch64] New sve_size_tsz_bhs iclass. Add sve_size_tsz_bhs iclass needed for sqxtnb and similar instructions. This iclass encodes one of three variants by the most significant bit set in a 3-bit value where only one bit may be set. include/ChangeLog: 2019-05-09 Matthew Malcomson * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_tsz_bhs iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_tsz_bhs iclass decode. --- include/opcode/aarch64.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/opcode') diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 25201cf..e354e65 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -601,6 +601,7 @@ enum aarch64_insn_class sve_size_013, sve_shift_tsz_hsd, sve_shift_tsz_bhsd, + sve_size_tsz_bhs, testbranch, cryptosm3, cryptosm4, -- cgit v1.1