From e5b06ef06b062f0626462abb182ee5470cf798bc Mon Sep 17 00:00:00 2001 From: Claudiu Zissulescu Date: Thu, 13 Oct 2016 15:01:19 +0200 Subject: [ARC] Disassembler: fix LIMM detection for short instructions. The ARC (short) instructions are using a special register number to indicate is the instruction uses a long immediate (LIMM). In the case of short instruction, this LIMM indicator depends on the ISA version used. Thus, for ARCv1 processors, the LIMM indicator is 0x3E, the same value used in "long" instructions. However, for the ARCv2 processors, this LIMM indicator is 0x1E. This patch fixes the LIMM detection for ARCv1 ISA and adds two tests. gas/ 2016-10-13 Claudiu Zissulescu * testsuite/gas/arc/shortlimm_a7.d: New file. * testsuite/gas/arc/shortlimm_a7.s: Likewise. * testsuite/gas/arc/shortlimm_hs.d: Likewise. * testsuite/gas/arc/shortlimm_hs.s: Likewise. include/ 2016-10-13 Claudiu Zissulescu * opcode/arc.h (ARC_OPCODE_ARCV2): New define. opcodes/ 2016-10-13 Claudiu Zissulescu * arc-dis.c (find_format_from_table): Discriminate LIMM indicator usage on ISA basis. --- include/opcode/arc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/opcode') diff --git a/include/opcode/arc.h b/include/opcode/arc.h index 09e973b..724fdee 100644 --- a/include/opcode/arc.h +++ b/include/opcode/arc.h @@ -186,6 +186,7 @@ extern const struct arc_opcode arc_opcodes[]; #define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS) #define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM) +#define ARC_OPCODE_ARCV2 (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS) /* CPU extensions. */ #define ARC_EA 0x0001 -- cgit v1.1