From dd6a37e700ab12b5f5e89b747992324e74981872 Mon Sep 17 00:00:00 2001 From: Andrew Pinski Date: Tue, 29 Nov 2011 20:28:55 +0000 Subject: opcode/ 2011-11-29 Andrew Pinski * mips-dis.c (mips_arch_choices): Add Octeon+. * mips-opc.c (IOCT): Include Octeon+. (IOCTP): New macro. (mips_builtin_opcodes): Add "saa" and "saad". bfd/ 2011-11-29 Andrew Pinski * archures.c (bfd_mach_mips_octeonp): New macro. * bfd-in2.h: Regenerate. * bfd/cpu-mips.c (I_mipsocteonp): New enum value. (arch_info_struct): Add bfd_mach_mips_octeonp. * elfxx-mips.c (mips_set_isa_flags): Add bfd_mach_mips_octeonp. (mips_mach_extensions): Add bfd_mach_mips_octeonp. include/opcodes/ 2011-11-29 Andrew Pinski * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP. (INSN_OCTEONP): New macro. (CPU_OCTEONP): New macro. (OPCODE_IS_MEMBER): Add Octeon+. (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values. gas/ 2011-11-29 Andrew Pinski * config/tc-mips.c (CPU_IS_OCTEON): New macro function. (CPU_HAS_SEQ): Change to use CPU_IS_OCTEON. (NO_ISA_COP): Likewise. (macro) : Add support when off0 is true. Add support for M_SAA_AB, M_SAA_OB, M_SAAD_OB and M_SAAD_AB. (mips_cpu_info_table): Add octeon+. * doc/c-mips.texi: Document octeon+ as an acceptable value for -march=. gas/testsuite/ 2011-11-29 Andrew Pinski * gas/mips/mips.exp: Add octeon+ for an architecture. Run octeon-saa-saad test. (run_dump_test_arch): For Octeon architectures, also try octeon@. * gas/mips/octeon-pref.d: Remove -march=octeon from command line. * gas/mips/octeon.d: Likewise. * gas/mips/octeon-saa-saad.d: New file. * gas/mips/octeon-saa-saad.s: New file --- include/opcode/ChangeLog | 8 ++++++++ include/opcode/mips.h | 10 +++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) (limited to 'include/opcode') diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index dd4a977..bfd71e0 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,11 @@ +2011-11-29 Andrew Pinski + + * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP. + (INSN_OCTEONP): New macro. + (CPU_OCTEONP): New macro. + (OPCODE_IS_MEMBER): Add Octeon+. + (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values. + 2011-11-01 DJ Delorie * rl78.h: New file. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index a94860f..eb28d16 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -713,10 +713,11 @@ static const unsigned int mips_isa_table[] = { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; /* Masks used for Chip specific instructions. */ -#define INSN_CHIP_MASK 0xc3ff0c20 +#define INSN_CHIP_MASK 0xc3ff0e20 /* Cavium Networks Octeon instructions. */ #define INSN_OCTEON 0x00000800 +#define INSN_OCTEONP 0x00000200 /* Masks used for MIPS-defined ASEs. */ #define INSN_ASE_MASK 0x3c00f010 @@ -823,6 +824,7 @@ static const unsigned int mips_isa_table[] = #define CPU_LOONGSON_2F 3002 #define CPU_LOONGSON_3A 3003 #define CPU_OCTEON 6501 +#define CPU_OCTEONP 6601 #define CPU_XLR 887682 /* decimal 'XLR' */ /* Test for membership in an ISA including chip specific ISAs. INSN @@ -859,6 +861,8 @@ static const unsigned int mips_isa_table[] = && ((insn)->membership & INSN_LOONGSON_3A) != 0) \ || (cpu == CPU_OCTEON \ && ((insn)->membership & INSN_OCTEON) != 0) \ + || (cpu == CPU_OCTEONP \ + && ((insn)->membership & INSN_OCTEONP) != 0) \ || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \ || 0) /* Please keep this term for easier source merging. */ @@ -1065,6 +1069,10 @@ enum M_S_DOB, M_S_DAB, M_S_S, + M_SAA_AB, + M_SAA_OB, + M_SAAD_AB, + M_SAAD_OB, M_SC_AB, M_SC_OB, M_SCD_AB, -- cgit v1.1