From c8d59609b1cf66eaff3c486e483f5e3d647c66ff Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Wed, 28 Mar 2018 09:44:45 +0100 Subject: Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+REG addressing with an assumed offset register. PR 22988 opcode * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_SVE_ADDR_R. opcodes * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx instructions with only a base address register. * aarch64-opc.c (operand_general_constraint_met_p): Add code to handle AARHC64_OPND_SVE_ADDR_R. (aarch64_print_operand): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64_dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas * config/tc-aarch64.c (parse_operands): Add code to handle AARCH64_OPN_SVE_ADDR_R. * testsuite/gas/aarch64/sve.s: Add tests for LDFF1xx instructions with an assumed XZR offset address register. * testsuite/gas/aarch64/sve.d: Update expected disassembly. --- include/opcode/aarch64.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/opcode') diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index a94d779..16c41bf 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -272,6 +272,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [, #*2]. */ AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [, #*4]. */ AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [, #*8]. */ + AARCH64_OPND_SVE_ADDR_R, /* SVE []. */ AARCH64_OPND_SVE_ADDR_RR, /* SVE [, ]. */ AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [, , LSL #1]. */ AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [, , LSL #2]. */ -- cgit v1.1