From c63af675b9b69abbbf5e48d7b77ec2d311c5b6a8 Mon Sep 17 00:00:00 2001 From: Jin Ma Date: Sat, 18 Nov 2023 15:07:00 +0800 Subject: RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extension MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds integer arithmetic instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for integer arithmetic instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VADCVVM): New. opcodes/ChangeLog: * riscv-opc.c: Likewise. --- include/opcode/riscv-opc.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include/opcode') diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 58618a4..df4b7ab 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2885,6 +2885,18 @@ #define MASK_TH_VAMOMAXUWV 0xf800707f #define MATCH_TH_VAMOMAXUDV 0xe000702f #define MASK_TH_VAMOMAXUDV 0xf800707f +#define MATCH_TH_VADCVVM 0x42000057 +#define MASK_TH_VADCVVM 0xfe00707f +#define MATCH_TH_VADCVXM 0x42004057 +#define MASK_TH_VADCVXM 0xfe00707f +#define MATCH_TH_VADCVIM 0x42003057 +#define MASK_TH_VADCVIM 0xfe00707f +#define MATCH_TH_VSBCVVM 0x4a000057 +#define MASK_TH_VSBCVVM 0xfe00707f +#define MATCH_TH_VSBCVXM 0x4a004057 +#define MASK_TH_VSBCVXM 0xfe00707f +#define MATCH_TH_VWMACCSUVV 0xf8002057 +#define MASK_TH_VWMACCSUVV 0xfc00707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f -- cgit v1.1