From af4bcb4ce6939da1738c847a06789d2223b67ca4 Mon Sep 17 00:00:00 2001 From: Sudakshina Das Date: Wed, 26 Sep 2018 10:57:16 +0100 Subject: [PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) The encodings can be found in the System Register XML. This patch adds the following: MSR Xn, RNDR MSR Xn, RNDRRS These are optional instructions in ARMv8.5-A and hence the new +rng is added. *** include/ChangeLog *** 2018-10-09 Sudakshina Das * opcode/aarch64.h (AARCH64_FEATURE_RNG): New. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das * aarch64-opc.c (aarch64_sys_regs): New entries for rndr and rndrrs. (aarch64_sys_reg_supported_p): New check for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das * config/tc-aarch64.c (aarch64_features): New "rng" option. * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/sysreg-4.s: Test both instructions. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise. --- include/opcode/aarch64.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/opcode') diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 7656a57..b4987de 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -74,6 +74,8 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_PREDRES 0x20000000000ULL /* DC CVADP. */ #define AARCH64_FEATURE_CVADP 0x40000000000ULL +/* Random Number instructions. */ +#define AARCH64_FEATURE_RNG 0x80000000000ULL /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ -- cgit v1.1