From 0952813b0b27abe7f53a8048c0218883412e54cd Mon Sep 17 00:00:00 2001 From: DJ Delorie Date: Thu, 30 Apr 2015 15:25:49 -0400 Subject: Make RL78 disassembler and simulator respect ISA for mul/div [gas] * config/rl78-defs.h (rl78_isa_g10): New. (rl78_isa_g13): New. (rl78_isa_g14): New. * config/rl78-parse.y (ISA_G10): New. (ISA_G13): New. (ISA_G14): New. (MULHU, MULH, MULU, DIVHU, DIVWU, MACHU, MACH): Use them. * config/tc-rl78.c (rl78_isa_g10): New. (rl78_isa_g13): New. (rl78_isa_g14): New. [gdb] * rl78-tdep.c (rl78_analyze_prologue): Pass RL78_ISA_DEFAULT to rl78_decode_opcode [include] * dis-asm.h (print_insn_rl78_g10): New. (print_insn_rl78_g13): New. (print_insn_rl78_g14): New. (rl78_get_disassembler): New. * opcode/rl78.h (RL78_Dis_Isa): New. (rl78_decode_opcode): Add ISA parameter. [opcodes] * disassemble.c (disassembler): Choose suitable disassembler based on E_ABI. * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use it to decode mul/div insns. * rl78-decode.c: Regenerate. * rl78-dis.c (print_insn_rl78): Rename to... (print_insn_rl78_common): ...this, take ISA parameter. (print_insn_rl78): New. (print_insn_rl78_g10): New. (print_insn_rl78_g13): New. (print_insn_rl78_g14): New. (rl78_get_disassembler): New. [sim] * rl78/cpu.c (g14_multiply): New. * rl78/cpu.h (g14_multiply): New. * rl78/load.c (rl78_load): Decode ISA completely. * rl78/main.c (main): Expand -M to include other ISAs. * rl78/rl78.c (decode_opcode): Decode based on ISA. * rl78/trace.c (rl78_disasm_fn): New. (sim_disasm_init): Reset it. (sim_disasm_one): Get correct disassembler for ISA. --- include/opcode/ChangeLog | 5 +++++ include/opcode/rl78.h | 9 ++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) (limited to 'include/opcode') diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 4a0534f..b5702c5 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,8 @@ +2015-04-30 DJ Delorie + + * rl78.h (RL78_Dis_Isa): New. + (rl78_decode_opcode): Add ISA parameter. + 2015-03-24 Terry Guo * arm.h (arm_feature_set): Extended to provide more available bits. diff --git a/include/opcode/rl78.h b/include/opcode/rl78.h index 72adf14..7358d2d 100644 --- a/include/opcode/rl78.h +++ b/include/opcode/rl78.h @@ -30,6 +30,13 @@ extern "C" { #endif +typedef enum { + RL78_ISA_DEFAULT, + RL78_ISA_G10, + RL78_ISA_G13, + RL78_ISA_G14, +} RL78_Dis_Isa; + /* For the purposes of these structures, the RL78 registers are as follows, despite most of these being memory-mapped and bank-switched: */ @@ -166,7 +173,7 @@ typedef struct RL78_Opcode_Operand op[2]; } RL78_Opcode_Decoded; -int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded *, int (*)(void *), void *); +int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded *, int (*)(void *), void *, RL78_Dis_Isa); #ifdef __cplusplus } -- cgit v1.1