From c60b3806799abf1d7f6cf5108a1b0e733a950b13 Mon Sep 17 00:00:00 2001 From: Jedidiah Thompson Date: Wed, 19 Oct 2022 10:57:12 +0200 Subject: aarch64-pe support for LD, GAS and BFD Allows aarch64-pe to be targeted natively, not having to use objcopy to convert it from ELF to PE. Based on initial work by Jedidiah Thompson Co-authored-by: Jedidiah Thompson Co-authored-by: Zac Walker --- include/coff/aarch64.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'include/coff') diff --git a/include/coff/aarch64.h b/include/coff/aarch64.h index 2bbeaa9..100e08f 100644 --- a/include/coff/aarch64.h +++ b/include/coff/aarch64.h @@ -60,4 +60,26 @@ struct external_reloc #define RELOC struct external_reloc #define RELSZ 14 +/* ARM64 relocations types. */ + + +#define IMAGE_REL_ARM64_ABSOLUTE 0x0000 /* No relocation required */ +#define IMAGE_REL_ARM64_ADDR32 0x0001 /* The 32-bit VA of the target. */ +#define IMAGE_REL_ARM64_ADDR32NB 0x0002 /* The 32-bit RVA of the target. */ +#define IMAGE_REL_ARM64_BRANCH26 0x0003 /* The 26-bit relative displacement to the target, for B and BL instructions. */ +#define IMAGE_REL_ARM64_PAGEBASE_REL21 0x0004 /* The page base of the target, for ADRP instruction. */ +#define IMAGE_REL_ARM64_REL21 0x0005 /* The 12-bit relative displacement to the target, for instruction ADR */ +#define IMAGE_REL_ARM64_PAGEOFFSET_12A 0x0006 /* The 12-bit page offset of the target, for instructions ADD/ADDS (immediate) with zero shift. */ +#define IMAGE_REL_ARM64_PAGEOFFSET_12L 0x0007 /* The 12-bit page offset of the target, for instruction LDR (indexed, unsigned immediate). */ +#define IMAGE_REL_ARM64_SECREL 0x0008 /* The 32-bit offset of the target from the beginning of its section. This is used to support debugging information and static thread local storage. */ +#define IMAGE_REL_ARM64_SECREL_LOW12A 0x0009 /* Bit 0:11 of section offset of the target, for instructions ADD/ADDS (immediate) with zero shift. */ +#define IMAGE_REL_ARM64_SECREL_HIGH12A 0x000A /* Bit 12:23 of section offset of the target, for instructions ADD/ADDS (immediate) with zero shift. */ +#define IMAGE_REL_ARM64_SECREL_LOW12L 0x000B /* Bit 0:11 of section offset of the target, for instruction LDR (indexed, unsigned immediate). */ +#define IMAGE_REL_ARM64_TOKEN 0x000C /* CLR token */ +#define IMAGE_REL_ARM64_SECTION 0x000D /* The 16-bit section index of the section that contains the target. This is used to support debugging information. */ +#define IMAGE_REL_ARM64_ADDR64 0x000E /* The 64-bit VA of the relocation target. */ +#define IMAGE_REL_ARM64_BRANCH19 0x000F /* 19 bit offset << 2 & sign ext. for conditional B */ +#define IMAGE_REL_ARM64_BRANCH14 0x0010 /* The 14-bit offset to the relocation target, for instructions TBZ and TBNZ. */ +#define IMAGE_REL_ARM64_REL32 0x0011 /* The 32-bit relative address from the byte following the relocation. */ + #define ARM_NOTE_SECTION ".note" -- cgit v1.1