From 604c2f837ca75dbfd0331a7d8a7f9504ca1d9b53 Mon Sep 17 00:00:00 2001
From: Luis Machado <luisgpm@br.ibm.com>
Date: Fri, 15 Aug 2008 15:18:34 +0000
Subject: * rs6000-tdep: Include "features/rs6000/powerpc-vsx32.c".
Include "features/rs6000/powerpc-vsx64.c". (ppc_supply_vsxregset): New
function. (ppc_collect_vsxregset): New function. (IS_VSX_PSEUDOREG):
New macro. (IS_EFP_PSEUDOREG): New macro. (vsx_register_p): New
function. (ppc_vsx_support_p): New function.
(rs6000_builtin_type_vec128): New function. (rs6000_register_name): Hide
upper halves of vs0~vs31. Return correct names for VSX registers and
EFPR registers. (rs6000_pseudo_register_type): Return correct types
for VSX and EFPR registers. (rs6000_pseudo_register_reggroup_p):
Return correct group for VSX and EFPR registers.
(ppc_pseudo_register_read): Rename to dfp_pseudo_register_read.
(ppc_pseudo_register_write): Rename to dfp_pseudo_register_write.
(vsx_pseudo_register_read): New function. (vsx_pseudo_register_write):
New function. (efpr_pseudo_register_read): New function.
(efpr_pseudo_register_write): New function. (rs6000_pseudo_register_read):
Call new VSX and EFPR read functions. (rs6000_pseudo_register_write): Call
new VSX and EFPR write functions. (rs6000_gdbarch_init): Declare
have_vsx. Initialize new upper half VSX registers. Initialize
VSX-related and EFPR-related pseudo-registers variables. Adjust the
number of pseudo registers accordingly.
* ppc-linux-nat.c: Define PTRACE_GETVSXREGS, PTRACE_SETVSXREGS
and SIZEOF_VSRREGS.
(gdb_vsxregset_t): New type.
(have_ptrace_getsetvsxregs): New variable.
(fetch_vsx_register): New function.
(fetch_register): Handle VSX registers.
(fetch_vsx_registers): New function.
(fetch_ppc_registers): Handle VSX registers.
(store_ppc_registers): Handle VSX registers.
(store_vsx_register): New function.
(store_register): Handle VSX registers.
(store_vsx_registers): New function.
(ppc_linux_read_description): Handle VSX-enabled inferiors.
(gdb_vsxregset_t): New type.
(supply_vsxregset): New function.
(fill_vsxregset): New function.
* ppc-tdep.h (vsx_register_p): New prototype.
(vsx_support_p): New prototype.
(ppc_vsr0_regnum): New variable.
(ppc_vsr0_upper_regnum): Likewise.
(ppc_efpr0_regnum): Likewise.
(ppc_builtin_type_vec128): New type.
(ppc_num_vsrs): New constant.
(ppc_num_vshrs): New constant.
(ppc_num_efprs): Likewise.
Define POWERPC_VEC_VSX PPC_VSR0_UPPER_REGNUM and PPC_VSR31_UPPER_REGNUM.
(ppc_supply_vsxregset): New prototype.
(ppc_collect_vsxregset): New prototype.
* ppc-linux-tdep.c: Include "features/rs6000/powerpc-vsx32l.c"
Include "features/rs6000/powerpc-vsx64l.c".
(_initialize_ppc_linux_tdep): Initialize VSX-enabled targets.
(ppc_linux_regset_sections): Add new ".reg-ppc-vsx" field.
(ppc32_linux_vsxregset): New 32-bit VSX-enabled regset.
(ppc_linux_regset_from_core_section): Handle VSX core section.
(ppc_linux_core_read_description): Support VSX-enabled core files.
* ppc-linux-tdep.h: Declare *tdesc_powerpc_vsx32l
Declare tdesc_powerpc_vsx64l
* corelow.c (get_core_register_section): Support VSX-enabled
core files.
* features/rs6000/power-vsx.xml: New VSX descriptions.
* features/rs6000/powerpc-vsx32.xml: New file.
* features/rs6000/powerpc-vsx32l.xml: New file.
* features/rs6000/powerpc-vsx64.xml: New file.
* features/rs6000/powerpc-vsx64l.xml: New file.
* features/rs6000/powerpc-vsx32.c: New file (generated).
* features/rs6000/powerpc-vsx32l.c: New file (generated).
* features/rs6000/powerpc-vsx64.c: New file (generated).
* features/rs6000/powerpc-vsx64l.c: New file (generated).
* features/Makefile: Updated with new descriptions.
* regformats/rs6000/powerpc-vsx32l.dat: New file (generated).
* regformats/rs6000/powerpc-vsx64l.dat: New file (generated).
* testsuite/gdb.arch/vsx-regs.c: New source file.
* testsuite/gdb.arch/vsx-regs.exp: New testcase.
* testsuite/lib/gdb.exp (skip_vsx_tests): New function.
---
gdb/testsuite/gdb.arch/vsx-regs.c | 41 ++++++++
gdb/testsuite/gdb.arch/vsx-regs.exp | 193 ++++++++++++++++++++++++++++++++++++
2 files changed, 234 insertions(+)
create mode 100644 gdb/testsuite/gdb.arch/vsx-regs.c
create mode 100644 gdb/testsuite/gdb.arch/vsx-regs.exp
(limited to 'gdb/testsuite/gdb.arch')
diff --git a/gdb/testsuite/gdb.arch/vsx-regs.c b/gdb/testsuite/gdb.arch/vsx-regs.c
new file mode 100644
index 0000000..24a6fa6
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/vsx-regs.c
@@ -0,0 +1,41 @@
+#include <altivec.h>
+#include <stdio.h>
+
+vector unsigned int
+vector_fun (vector unsigned int a, vector unsigned int b)
+{
+ vector unsigned int c;
+ a = ((vector unsigned int) vec_splat_u8(2));
+ b = ((vector unsigned int) vec_splat_u8(3));
+
+ c = vec_add (a, b);
+ return c;
+}
+
+int
+main ()
+{
+ vector unsigned int y;
+ vector unsigned int x;
+ vector unsigned int z;
+ int a;
+
+ /* This line may look unnecessary but we do need it, because we want to
+ have a line to do a next over (so that gdb refetches the registers)
+ and we don't want the code to change any vector registers.
+ The splat operations below modify the VRs,i
+ so we don't want to execute them yet. */
+ a = 9;
+ x = ((vector unsigned int) vec_splat_u8 (-2));
+ y = ((vector unsigned int) vec_splat_u8 (1));
+
+ z = vector_fun (x, y);
+ x = vec_sld (x,y,2);
+
+ x = vec_add (x, ((vector unsigned int){5,6,7,8}));
+ z = (vector unsigned int) vec_splat_u8 ( -2);
+ y = vec_add (x, z);
+ z = (vector unsigned int) vec_cmpeq (x,y);
+
+ return 0;
+}
diff --git a/gdb/testsuite/gdb.arch/vsx-regs.exp b/gdb/testsuite/gdb.arch/vsx-regs.exp
new file mode 100644
index 0000000..006eb6d
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/vsx-regs.exp
@@ -0,0 +1,193 @@
+# Copyright (C) 2008 Free Software Foundation, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# Please email any bugs, comments, and/or additions to this file to:
+# bug-gdb@prep.ai.mit.edu
+#
+
+# Tests for Powerpc AltiVec register setting and fetching
+
+if $tracelevel then {
+ strace $tracelevel
+}
+
+#
+# Test the use of VSX registers, for Powerpc.
+#
+
+set prms_id 0
+set bug_id 0
+
+if {![istarget "powerpc*"] || [skip_vsx_tests]} then {
+ verbose "Skipping vsx register tests."
+ verbose -log "Skipping vsx register tests."
+ return
+}
+
+set testfile "vsx-regs"
+set binfile ${objdir}/${subdir}/${testfile}
+set srcfile ${testfile}.c
+
+set compile_flags {debug nowarnings quiet}
+if [get_compiler_info $binfile] {
+ warning "get_compiler failed"
+ return -1
+}
+
+if [test_compiler_info gcc*] {
+ set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec"
+} elseif [test_compiler_info xlc*] {
+ set compile_flags "$compile_flags additional_flags=-qaltivec"
+} else {
+ warning "unknown compiler"
+ return -1
+}
+
+if { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } {
+ untested vsx-regs.exp
+ return -1
+}
+
+gdb_start
+gdb_reinitialize_dir $srcdir/$subdir
+gdb_load ${binfile}
+
+# Run to `main' where we begin our tests.
+
+if ![runto_main] then {
+ gdb_suppress_tests
+}
+
+# Data sets used throughout the test
+
+set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
+
+set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
+
+set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
+
+set float_register ".raw 0xdeadbeefdeadbeef."
+
+# First run the F0~F31/VS0~VS31 tests
+
+# 1: Set F0~F31 registers and check if it reflects on VS0~VS31.
+for {set i 0} {$i < 32} {incr i 1} {
+ send_gdb "set \$f$i = 1\.3"
+}
+
+for {set i 0} {$i < 32} {incr i 1} {
+ gdb_test "info reg vs$i" "vs$i.*$vector_register1" "info reg vs$i (doubleword 0)"
+}
+
+# 2: Set VS0~VS31 registers and check if it reflects on F0~F31.
+for {set i 0} {$i < 32} {incr i 1} {
+ for {set j 0} {$j < 4} {incr j 1} {
+ send_gdb "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef"
+ }
+}
+
+for {set i 0} {$i < 32} {incr i 1} {
+ gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
+}
+
+for {set i 0} {$i < 32} {incr i 1} {
+ gdb_test "info reg vs$i" "vs$i.*$vector_register2" "info reg vs$i (doubleword 1)"
+}
+
+# Now run the VR0~VR31/VS32~VS63 tests
+
+# 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63.
+for {set i 0} {$i < 32} {incr i 1} {
+ for {set j 0} {$j < 4} {incr j 1} {
+ send_gdb "set \$vr$i.v4_int32\[$j\] = 1"
+ }
+}
+
+for {set i 32} {$i < 64} {incr i 1} {
+ gdb_test "info reg vs$i" "vs$i.*$vector_register3" "info reg vs$i"
+}
+# 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31.
+for {set i 32} {$i < 64} {incr i 1} {
+ for {set j 0} {$j < 4} {incr j 1} {
+ send_gdb "set \$vs$i.v4_int32\[$j\] = 1"
+ }
+}
+
+for {set i 0} {$i < 32} {incr i 1} {
+ gdb_test "info reg vr$i" "vr$i.*$vector_register3" "info reg vr$i"
+}
+
+set escapedfilename [string_to_regexp ${objdir}/${subdir}/vsx-core.test]
+
+set core_supported 0
+
+gdb_test_multiple "gcore ${objdir}/${subdir}/vsx-core.test" \
+ "Save a VSX-enabled corefile" \
+{
+ -re "Saved corefile ${escapedfilename}\[\r\n\]+$gdb_prompt $" {
+ pass "Save a VSX-enabled corefile"
+ global core_supported
+ set core_supported 1
+ }
+ -re "Can't create a corefile\[\r\n\]+$gdb_prompt $" {
+ unsupported "Save a VSX-enabled corefile"
+ global core_supported
+ set core_supported 0
+ }
+}
+
+if {!$core_supported} {
+ return -1
+}
+
+gdb_exit
+gdb_start
+gdb_reinitialize_dir $srcdir/$subdir
+gdb_load ${binfile}
+
+gdb_test_multiple "core ${objdir}/${subdir}/vsx-core.test" \
+ "re-load generated corefile" \
+{
+ -re ".* is not a core dump:.*$gdb_prompt $" {
+ fail "re-load generated corefile (bad file format)"
+ # No use proceeding from here.
+ return;
+ }
+ -re ".*: No such file or directory.*$gdb_prompt $" {
+ fail "re-load generated corefile (file not found)"
+ # No use proceeding from here.
+ return;
+ }
+ -re ".*Couldn't find .* registers in core file.*$gdb_prompt $" {
+ fail "re-load generated corefile (incomplete note section)"
+ }
+ -re "Core was generated by .*$gdb_prompt $" {
+ pass "re-load generated corefile"
+ }
+ -re ".*$gdb_prompt $" {
+ fail "re-load generated corefile"
+ }
+ timeout {
+ fail "re-load generated corefile (timeout)"
+ }
+}
+
+for {set i 0} {$i < 32} {incr i 1} {
+ gdb_test "info reg vs$i" "vs$i.*$vector_register2" "Restore vs$i from core file"
+}
+
+for {set i 32} {$i < 64} {incr i 1} {
+ gdb_test "info reg vs$i" "vs$i.*$vector_register3" "Restore vs$i from core file"
+}
--
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