From 8a61382623e271fe2df0fe8f7558ea545db8b561 Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Fri, 26 Oct 2018 10:29:46 -0700 Subject: RISC-V: Linux signal frame support. Make riscv_isa_flen available to the linux native code, and clean up duplicate comments. gdb/ * riscv-tdep.c (riscv_isa_xlen): Refer to riscv-tdep.h comment. (riscv_isa_flen): Likewise. Drop static. * riscv-tdep.h (riscv_isa_xlen): Move riscv-tdep.c comment to here. (riscv_isa_flen): Likewise. --- gdb/riscv-tdep.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'gdb/riscv-tdep.c') diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index e4b35a0..4b5f38a 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -349,9 +349,7 @@ riscv_has_feature (struct gdbarch *gdbarch, char feature) return (misa & (1 << (feature - 'A'))) != 0; } -/* Return the width in bytes of the general purpose registers for GDBARCH. - Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or - RV128. */ +/* See riscv-tdep.h. */ int riscv_isa_xlen (struct gdbarch *gdbarch) @@ -370,12 +368,9 @@ riscv_isa_xlen (struct gdbarch *gdbarch) } } -/* Return the width in bytes of the floating point registers for GDBARCH. - If this architecture has no floating point registers, then return 0. - Possible values are 4, 8, or 16 for depending on which of single, double - or quad floating point support is available. */ +/* See riscv-tdep.h. */ -static int +int riscv_isa_flen (struct gdbarch *gdbarch) { if (riscv_has_feature (gdbarch, 'Q')) -- cgit v1.1