From df7e526582809b829ee8651a1315a17627cfea4d Mon Sep 17 00:00:00 2001 From: Gary Benson Date: Tue, 19 Aug 2014 15:16:11 +0100 Subject: Rename 32- and 64-bit Intel files from "i386" to "x86" This commit renames nine files that contain code used by both 32- and 64-bit Intel ports such that their names are prefixed with "x86" rather than "i386". All types, functions and variables within these files are likewise renamed such that their names are prefixed with "x86" rather than "i386". This makes GDB follow the convention used by gdbserver such that 32-bit Intel code lives in files called "i386-*", 64-bit Intel code lives in files called "amd64-*", and code for both 32- and 64-bit Intel lives in files called "x86-*". This commit only renames OS-independent files. The Linux ports of both GDB and gdbserver now follow the i386/amd64/x86 convention fully. Some ports still use the old convention where "i386" in file/function/ type/variable names can mean "32-bit only" or "32- and 64-bit" but I don't want to touch ports I can't fully test except where absolutely necessary. gdb/ChangeLog: * i386-nat.h: Renamed as... * x86-nat.h: New file. All type, function and variable name prefixes changed from "i386_" to "x86_". All references updated. * i386-nat.c: Renamed as... * x86-nat.c: New file. All type, function and variable name prefixes changed from "i386_" to "x86_". All references updated. * common/i386-xstate.h: Renamed as... * common/x86-xstate.h: New file. All type, function and variable name prefixes changed from "i386_" to "x86_". All references updated. * nat/i386-cpuid.h: Renamed as... * nat/x86-cpuid.h: New file. All type, function and variable name prefixes changed from "i386_" to "x86_". All references updated. * nat/i386-gcc-cpuid.h: Renamed as... * nat/x86-gcc-cpuid.h: New file. All type, function and variable name prefixes changed from "i386_" to "x86_". All references updated. * nat/i386-dregs.h: Renamed as... * nat/x86-dregs.h: New file. All type, function and variable name prefixes changed from "i386_" to "x86_". All references updated. * nat/i386-dregs.c: Renamed as... * nat/x86-dregs.c: New file. All type, function and variable name prefixes changed from "i386_" to "x86_". All references updated. gdb/gdbserver/ChangeLog: * i386-low.h: Renamed as... * x86-low.h: New file. All type, function and variable name prefixes changed from "i386_" to "x86_". All references updated. * i386-low.c: Renamed as... * x86-low.c: New file. All type, function and variable name prefixes changed from "i386_" to "x86_". All references updated. --- gdb/nat/i386-cpuid.h | 63 ----- gdb/nat/i386-dregs.c | 664 ----------------------------------------------- gdb/nat/i386-dregs.h | 126 --------- gdb/nat/i386-gcc-cpuid.h | 278 -------------------- gdb/nat/linux-btrace.c | 6 +- gdb/nat/x86-cpuid.h | 63 +++++ gdb/nat/x86-dregs.c | 664 +++++++++++++++++++++++++++++++++++++++++++++++ gdb/nat/x86-dregs.h | 126 +++++++++ gdb/nat/x86-gcc-cpuid.h | 278 ++++++++++++++++++++ 9 files changed, 1134 insertions(+), 1134 deletions(-) delete mode 100644 gdb/nat/i386-cpuid.h delete mode 100644 gdb/nat/i386-dregs.c delete mode 100644 gdb/nat/i386-dregs.h delete mode 100644 gdb/nat/i386-gcc-cpuid.h create mode 100644 gdb/nat/x86-cpuid.h create mode 100644 gdb/nat/x86-dregs.c create mode 100644 gdb/nat/x86-dregs.h create mode 100644 gdb/nat/x86-gcc-cpuid.h (limited to 'gdb/nat') diff --git a/gdb/nat/i386-cpuid.h b/gdb/nat/i386-cpuid.h deleted file mode 100644 index 9aea054..0000000 --- a/gdb/nat/i386-cpuid.h +++ /dev/null @@ -1,63 +0,0 @@ -/* C API for x86 cpuid insn. - Copyright (C) 2007-2014 Free Software Foundation, Inc. - - This file is part of GDB. - - This file is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published by the - Free Software Foundation; either version 3, or (at your option) any - later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -#ifndef I386_CPUID_COMMON_H -#define I386_CPUID_COMMON_H - -/* Always include the header for the cpu bit defines. */ -#include "i386-gcc-cpuid.h" - -#if defined(__i386__) || defined(__x86_64__) - -/* Return cpuid data for requested cpuid level, as found in returned - eax, ebx, ecx and edx registers. The function checks if cpuid is - supported and returns 1 for valid cpuid information or 0 for - unsupported cpuid level. Pointers may be non-null. */ - -static __inline int -i386_cpuid (unsigned int __level, - unsigned int *__eax, unsigned int *__ebx, - unsigned int *__ecx, unsigned int *__edx) -{ - unsigned int __scratch; - - if (!__eax) - __eax = &__scratch; - if (!__ebx) - __ebx = &__scratch; - if (!__ecx) - __ecx = &__scratch; - if (!__edx) - __edx = &__scratch; - - return __get_cpuid (__level, __eax, __ebx, __ecx, __edx); -} - -#else - -static __inline int -i386_cpuid (unsigned int __level, - unsigned int *__eax, unsigned int *__ebx, - unsigned int *__ecx, unsigned int *__edx) -{ - return 0; -} - -#endif /* i386 && x86_64 */ - -#endif /* I386_CPUID_COMMON_H */ diff --git a/gdb/nat/i386-dregs.c b/gdb/nat/i386-dregs.c deleted file mode 100644 index e3272cd..0000000 --- a/gdb/nat/i386-dregs.c +++ /dev/null @@ -1,664 +0,0 @@ -/* Debug register code for the i386. - - Copyright (C) 2001-2014 Free Software Foundation, Inc. - - This file is part of GDB. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -#ifdef GDBSERVER -#include "server.h" -#else -#include "defs.h" -#include "inferior.h" -#endif -#include "i386-dregs.h" - -/* Support for hardware watchpoints and breakpoints using the i386 - debug registers. - - This provides several functions for inserting and removing - hardware-assisted breakpoints and watchpoints, testing if one or - more of the watchpoints triggered and at what address, checking - whether a given region can be watched, etc. - - The functions below implement debug registers sharing by reference - counts, and allow to watch regions up to 16 bytes long. */ - -/* Accessor macros for low-level function vector. */ - -/* Can we update the inferior's debug registers? */ -#define i386_dr_low_can_set_addr() (i386_dr_low.set_addr != NULL) - -/* Update the inferior's debug register REGNUM from STATE. */ -#define i386_dr_low_set_addr(new_state, i) \ - (i386_dr_low.set_addr ((i), (new_state)->dr_mirror[(i)])) - -/* Return the inferior's debug register REGNUM. */ -#define i386_dr_low_get_addr(i) (i386_dr_low.get_addr ((i))) - -/* Can we update the inferior's DR7 control register? */ -#define i386_dr_low_can_set_control() (i386_dr_low.set_control != NULL) - -/* Update the inferior's DR7 debug control register from STATE. */ -#define i386_dr_low_set_control(new_state) \ - (i386_dr_low.set_control ((new_state)->dr_control_mirror)) - -/* Return the value of the inferior's DR7 debug control register. */ -#define i386_dr_low_get_control() (i386_dr_low.get_control ()) - -/* Return the value of the inferior's DR6 debug status register. */ -#define i386_dr_low_get_status() (i386_dr_low.get_status ()) - -/* Return the debug register size, in bytes. */ -#define i386_get_debug_register_length() \ - (i386_dr_low.debug_register_length) - -/* Support for 8-byte wide hw watchpoints. */ -#define TARGET_HAS_DR_LEN_8 (i386_get_debug_register_length () == 8) - -/* DR7 Debug Control register fields. */ - -/* How many bits to skip in DR7 to get to R/W and LEN fields. */ -#define DR_CONTROL_SHIFT 16 -/* How many bits in DR7 per R/W and LEN field for each watchpoint. */ -#define DR_CONTROL_SIZE 4 - -/* Watchpoint/breakpoint read/write fields in DR7. */ -#define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ -#define DR_RW_WRITE (0x1) /* Break on data writes. */ -#define DR_RW_READ (0x3) /* Break on data reads or writes. */ - -/* This is here for completeness. No platform supports this - functionality yet (as of March 2001). Note that the DE flag in the - CR4 register needs to be set to support this. */ -#ifndef DR_RW_IORW -#define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ -#endif - -/* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift - is so we could OR this with the read/write field defined above. */ -#define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ -#define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ -#define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ -#define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ - -/* Local and Global Enable flags in DR7. - - When the Local Enable flag is set, the breakpoint/watchpoint is - enabled only for the current task; the processor automatically - clears this flag on every task switch. When the Global Enable flag - is set, the breakpoint/watchpoint is enabled for all tasks; the - processor never clears this flag. - - Currently, all watchpoint are locally enabled. If you need to - enable them globally, read the comment which pertains to this in - i386_insert_aligned_watchpoint below. */ -#define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ -#define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ -#define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ - -/* Local and global exact breakpoint enable flags (a.k.a. slowdown - flags). These are only required on i386, to allow detection of the - exact instruction which caused a watchpoint to break; i486 and - later processors do that automatically. We set these flags for - backwards compatibility. */ -#define DR_LOCAL_SLOWDOWN (0x100) -#define DR_GLOBAL_SLOWDOWN (0x200) - -/* Fields reserved by Intel. This includes the GD (General Detect - Enable) flag, which causes a debug exception to be generated when a - MOV instruction accesses one of the debug registers. - - FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ -#define DR_CONTROL_RESERVED (0xFC00) - -/* Auxiliary helper macros. */ - -/* A value that masks all fields in DR7 that are reserved by Intel. */ -#define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) - -/* The I'th debug register is vacant if its Local and Global Enable - bits are reset in the Debug Control register. */ -#define I386_DR_VACANT(state, i) \ - (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) - -/* Locally enable the break/watchpoint in the I'th debug register. */ -#define I386_DR_LOCAL_ENABLE(state, i) \ - do { \ - (state)->dr_control_mirror |= \ - (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ - } while (0) - -/* Globally enable the break/watchpoint in the I'th debug register. */ -#define I386_DR_GLOBAL_ENABLE(state, i) \ - do { \ - (state)->dr_control_mirror |= \ - (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ - } while (0) - -/* Disable the break/watchpoint in the I'th debug register. */ -#define I386_DR_DISABLE(state, i) \ - do { \ - (state)->dr_control_mirror &= \ - ~(3 << (DR_ENABLE_SIZE * (i))); \ - } while (0) - -/* Set in DR7 the RW and LEN fields for the I'th debug register. */ -#define I386_DR_SET_RW_LEN(state, i, rwlen) \ - do { \ - (state)->dr_control_mirror &= \ - ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ - (state)->dr_control_mirror |= \ - ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ - } while (0) - -/* Get from DR7 the RW and LEN fields for the I'th debug register. */ -#define I386_DR_GET_RW_LEN(dr7, i) \ - (((dr7) \ - >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) - -/* Did the watchpoint whose address is in the I'th register break? */ -#define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i))) - -/* Types of operations supported by i386_handle_nonaligned_watchpoint. */ -typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; - -#ifndef GDBSERVER -/* Whether or not to print the mirrored debug registers. */ -extern int debug_hw_points; -#endif - -/* Print the values of the mirrored debug registers. */ - -static void -i386_show_dr (struct i386_debug_reg_state *state, - const char *func, CORE_ADDR addr, - int len, enum target_hw_bp_type type) -{ - int i; - - debug_printf ("%s", func); - if (addr || len) - debug_printf (" (addr=%s, len=%d, type=%s)", - phex (addr, 8), len, - type == hw_write ? "data-write" - : (type == hw_read ? "data-read" - : (type == hw_access ? "data-read/write" - : (type == hw_execute ? "instruction-execute" - /* FIXME: if/when I/O read/write - watchpoints are supported, add them - here. */ - : "??unknown??")))); - debug_printf (":\n"); - debug_printf ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", - phex (state->dr_control_mirror, 8), - phex (state->dr_status_mirror, 8)); - ALL_DEBUG_REGISTERS (i) - { - debug_printf ("\ -\tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", - i, phex (state->dr_mirror[i], - i386_get_debug_register_length ()), - state->dr_ref_count[i], - i + 1, phex (state->dr_mirror[i + 1], - i386_get_debug_register_length ()), - state->dr_ref_count[i + 1]); - i++; - } -} - -/* Return the value of a 4-bit field for DR7 suitable for watching a - region of LEN bytes for accesses of type TYPE. LEN is assumed to - have the value of 1, 2, or 4. */ - -static unsigned -i386_length_and_rw_bits (int len, enum target_hw_bp_type type) -{ - unsigned rw; - - switch (type) - { - case hw_execute: - rw = DR_RW_EXECUTE; - break; - case hw_write: - rw = DR_RW_WRITE; - break; - case hw_read: - internal_error (__FILE__, __LINE__, - _("The i386 doesn't support " - "data-read watchpoints.\n")); - case hw_access: - rw = DR_RW_READ; - break; -#if 0 - /* Not yet supported. */ - case hw_io_access: - rw = DR_RW_IORW; - break; -#endif - default: - internal_error (__FILE__, __LINE__, _("\ -Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"), - (int) type); - } - - switch (len) - { - case 1: - return (DR_LEN_1 | rw); - case 2: - return (DR_LEN_2 | rw); - case 4: - return (DR_LEN_4 | rw); - case 8: - if (TARGET_HAS_DR_LEN_8) - return (DR_LEN_8 | rw); - /* ELSE FALL THROUGH */ - default: - internal_error (__FILE__, __LINE__, _("\ -Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len); - } -} - -/* Insert a watchpoint at address ADDR, which is assumed to be aligned - according to the length of the region to watch. LEN_RW_BITS is the - value of the bits from DR7 which describes the length and access - type of the region to be watched by this watchpoint. Return 0 on - success, -1 on failure. */ - -static int -i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state, - CORE_ADDR addr, unsigned len_rw_bits) -{ - int i; - - if (!i386_dr_low_can_set_addr () || !i386_dr_low_can_set_control ()) - return -1; - - /* First, look for an occupied debug register with the same address - and the same RW and LEN definitions. If we find one, we can - reuse it for this watchpoint as well (and save a register). */ - ALL_DEBUG_REGISTERS (i) - { - if (!I386_DR_VACANT (state, i) - && state->dr_mirror[i] == addr - && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) - { - state->dr_ref_count[i]++; - return 0; - } - } - - /* Next, look for a vacant debug register. */ - ALL_DEBUG_REGISTERS (i) - { - if (I386_DR_VACANT (state, i)) - break; - } - - /* No more debug registers! */ - if (i >= DR_NADDR) - return -1; - - /* Now set up the register I to watch our region. */ - - /* Record the info in our local mirrored array. */ - state->dr_mirror[i] = addr; - state->dr_ref_count[i] = 1; - I386_DR_SET_RW_LEN (state, i, len_rw_bits); - /* Note: we only enable the watchpoint locally, i.e. in the current - task. Currently, no i386 target allows or supports global - watchpoints; however, if any target would want that in the - future, GDB should probably provide a command to control whether - to enable watchpoints globally or locally, and the code below - should use global or local enable and slow-down flags as - appropriate. */ - I386_DR_LOCAL_ENABLE (state, i); - state->dr_control_mirror |= DR_LOCAL_SLOWDOWN; - state->dr_control_mirror &= I386_DR_CONTROL_MASK; - - return 0; -} - -/* Remove a watchpoint at address ADDR, which is assumed to be aligned - according to the length of the region to watch. LEN_RW_BITS is the - value of the bits from DR7 which describes the length and access - type of the region watched by this watchpoint. Return 0 on - success, -1 on failure. */ - -static int -i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state, - CORE_ADDR addr, unsigned len_rw_bits) -{ - int i, retval = -1; - int all_vacant = 1; - - ALL_DEBUG_REGISTERS (i) - { - if (!I386_DR_VACANT (state, i) - && state->dr_mirror[i] == addr - && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) - { - if (--state->dr_ref_count[i] == 0) /* No longer in use? */ - { - /* Reset our mirror. */ - state->dr_mirror[i] = 0; - I386_DR_DISABLE (state, i); - /* Even though not strictly necessary, clear out all - bits in DR_CONTROL related to this debug register. - Debug output is clearer when we don't have stale bits - in place. This also allows the assertion below. */ - I386_DR_SET_RW_LEN (state, i, 0); - } - retval = 0; - } - - if (!I386_DR_VACANT (state, i)) - all_vacant = 0; - } - - if (all_vacant) - { - /* Even though not strictly necessary, clear out all of - DR_CONTROL, so that when we have no debug registers in use, - we end up with DR_CONTROL == 0. The Linux support relies on - this for an optimization. Plus, it makes for clearer debug - output. */ - state->dr_control_mirror &= ~DR_LOCAL_SLOWDOWN; - - gdb_assert (state->dr_control_mirror == 0); - } - return retval; -} - -/* Insert or remove a (possibly non-aligned) watchpoint, or count the - number of debug registers required to watch a region at address - ADDR whose length is LEN for accesses of type TYPE. Return 0 on - successful insertion or removal, a positive number when queried - about the number of registers, or -1 on failure. If WHAT is not a - valid value, bombs through internal_error. */ - -static int -i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, - i386_wp_op_t what, CORE_ADDR addr, int len, - enum target_hw_bp_type type) -{ - int retval = 0; - int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; - - static const int size_try_array[8][8] = - { - {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ - {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ - {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ - {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ - {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ - {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ - {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ - {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ - }; - - while (len > 0) - { - int align = addr % max_wp_len; - /* Four (eight on AMD64) is the maximum length a debug register - can watch. */ - int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); - int size = size_try_array[try][align]; - - if (what == WP_COUNT) - { - /* size_try_array[] is defined such that each iteration - through the loop is guaranteed to produce an address and a - size that can be watched with a single debug register. - Thus, for counting the registers required to watch a - region, we simply need to increment the count on each - iteration. */ - retval++; - } - else - { - unsigned len_rw = i386_length_and_rw_bits (size, type); - - if (what == WP_INSERT) - retval = i386_insert_aligned_watchpoint (state, addr, len_rw); - else if (what == WP_REMOVE) - retval = i386_remove_aligned_watchpoint (state, addr, len_rw); - else - internal_error (__FILE__, __LINE__, _("\ -Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"), - (int) what); - if (retval) - break; - } - - addr += size; - len -= size; - } - - return retval; -} - -/* Update the inferior debug registers state, in STATE, with the - new debug registers state, in NEW_STATE. */ - -static void -i386_update_inferior_debug_regs (struct i386_debug_reg_state *state, - struct i386_debug_reg_state *new_state) -{ - int i; - - ALL_DEBUG_REGISTERS (i) - { - if (I386_DR_VACANT (new_state, i) != I386_DR_VACANT (state, i)) - i386_dr_low_set_addr (new_state, i); - else - gdb_assert (new_state->dr_mirror[i] == state->dr_mirror[i]); - } - - if (new_state->dr_control_mirror != state->dr_control_mirror) - i386_dr_low_set_control (new_state); - - *state = *new_state; -} - -/* Insert a watchpoint to watch a memory region which starts at - address ADDR and whose length is LEN bytes. Watch memory accesses - of the type TYPE. Return 0 on success, -1 on failure. */ - -int -i386_dr_insert_watchpoint (struct i386_debug_reg_state *state, - enum target_hw_bp_type type, - CORE_ADDR addr, int len) -{ - int retval; - /* Work on a local copy of the debug registers, and on success, - commit the change back to the inferior. */ - struct i386_debug_reg_state local_state = *state; - - if (type == hw_read) - return 1; /* unsupported */ - - if (((len != 1 && len != 2 && len != 4) - && !(TARGET_HAS_DR_LEN_8 && len == 8)) - || addr % len != 0) - { - retval = i386_handle_nonaligned_watchpoint (&local_state, - WP_INSERT, - addr, len, type); - } - else - { - unsigned len_rw = i386_length_and_rw_bits (len, type); - - retval = i386_insert_aligned_watchpoint (&local_state, - addr, len_rw); - } - - if (retval == 0) - i386_update_inferior_debug_regs (state, &local_state); - - if (debug_hw_points) - i386_show_dr (state, "insert_watchpoint", addr, len, type); - - return retval; -} - -/* Remove a watchpoint that watched the memory region which starts at - address ADDR, whose length is LEN bytes, and for accesses of the - type TYPE. Return 0 on success, -1 on failure. */ - -int -i386_dr_remove_watchpoint (struct i386_debug_reg_state *state, - enum target_hw_bp_type type, - CORE_ADDR addr, int len) -{ - int retval; - /* Work on a local copy of the debug registers, and on success, - commit the change back to the inferior. */ - struct i386_debug_reg_state local_state = *state; - - if (((len != 1 && len != 2 && len != 4) - && !(TARGET_HAS_DR_LEN_8 && len == 8)) - || addr % len != 0) - { - retval = i386_handle_nonaligned_watchpoint (&local_state, - WP_REMOVE, - addr, len, type); - } - else - { - unsigned len_rw = i386_length_and_rw_bits (len, type); - - retval = i386_remove_aligned_watchpoint (&local_state, - addr, len_rw); - } - - if (retval == 0) - i386_update_inferior_debug_regs (state, &local_state); - - if (debug_hw_points) - i386_show_dr (state, "remove_watchpoint", addr, len, type); - - return retval; -} - -/* Return non-zero if we can watch a memory region that starts at - address ADDR and whose length is LEN bytes. */ - -int -i386_dr_region_ok_for_watchpoint (struct i386_debug_reg_state *state, - CORE_ADDR addr, int len) -{ - int nregs; - - /* Compute how many aligned watchpoints we would need to cover this - region. */ - nregs = i386_handle_nonaligned_watchpoint (state, WP_COUNT, - addr, len, hw_write); - return nregs <= DR_NADDR ? 1 : 0; -} - -/* If the inferior has some break/watchpoint that triggered, set the - address associated with that break/watchpoint and return non-zero. - Otherwise, return zero. */ - -int -i386_dr_stopped_data_address (struct i386_debug_reg_state *state, - CORE_ADDR *addr_p) -{ - CORE_ADDR addr = 0; - int i; - int rc = 0; - /* The current thread's DR_STATUS. We always need to read this to - check whether some watchpoint caused the trap. */ - unsigned status; - /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a - data breakpoint trap. Only fetch it when necessary, to avoid an - unnecessary extra syscall when no watchpoint triggered. */ - int control_p = 0; - unsigned control = 0; - - /* In non-stop/async, threads can be running while we change the - global dr_mirror (and friends). Say, we set a watchpoint, and - let threads resume. Now, say you delete the watchpoint, or - add/remove watchpoints such that dr_mirror changes while threads - are running. On targets that support non-stop, - inserting/deleting watchpoints updates the global dr_mirror only. - It does not update the real thread's debug registers; that's only - done prior to resume. Instead, if threads are running when the - mirror changes, a temporary and transparent stop on all threads - is forced so they can get their copy of the debug registers - updated on re-resume. Now, say, a thread hit a watchpoint before - having been updated with the new dr_mirror contents, and we - haven't yet handled the corresponding SIGTRAP. If we trusted - dr_mirror below, we'd mistake the real trapped address (from the - last time we had updated debug registers in the thread) with - whatever was currently in dr_mirror. So to fix this, dr_mirror - always represents intention, what we _want_ threads to have in - debug registers. To get at the address and cause of the trap, we - need to read the state the thread still has in its debug - registers. - - In sum, always get the current debug register values the current - thread has, instead of trusting the global mirror. If the thread - was running when we last changed watchpoints, the mirror no - longer represents what was set in this thread's debug - registers. */ - status = i386_dr_low_get_status (); - - ALL_DEBUG_REGISTERS (i) - { - if (!I386_DR_WATCH_HIT (status, i)) - continue; - - if (!control_p) - { - control = i386_dr_low_get_control (); - control_p = 1; - } - - /* This second condition makes sure DRi is set up for a data - watchpoint, not a hardware breakpoint. The reason is that - GDB doesn't call the target_stopped_data_address method - except for data watchpoints. In other words, I'm being - paranoiac. */ - if (I386_DR_GET_RW_LEN (control, i) != 0) - { - addr = i386_dr_low_get_addr (i); - rc = 1; - if (debug_hw_points) - i386_show_dr (state, "watchpoint_hit", addr, -1, hw_write); - } - } - - if (debug_hw_points && addr == 0) - i386_show_dr (state, "stopped_data_addr", 0, 0, hw_write); - - if (rc) - *addr_p = addr; - return rc; -} - -/* Return non-zero if the inferior has some watchpoint that triggered. - Otherwise return zero. */ - -int -i386_dr_stopped_by_watchpoint (struct i386_debug_reg_state *state) -{ - CORE_ADDR addr = 0; - return i386_dr_stopped_data_address (state, &addr); -} diff --git a/gdb/nat/i386-dregs.h b/gdb/nat/i386-dregs.h deleted file mode 100644 index 16edf63..0000000 --- a/gdb/nat/i386-dregs.h +++ /dev/null @@ -1,126 +0,0 @@ -/* Debug register code for the i386. - - Copyright (C) 2009-2014 Free Software Foundation, Inc. - - This file is part of GDB. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -/* Support for hardware watchpoints and breakpoints using the i386 - debug registers. - - This provides several functions for inserting and removing - hardware-assisted breakpoints and watchpoints, testing if one or - more of the watchpoints triggered and at what address, checking - whether a given region can be watched, etc. - - The functions below implement debug registers sharing by reference - counts, and allow to watch regions up to 16 bytes long - (32 bytes on 64 bit hosts). */ - -#ifndef I386_DREGS_H -#define I386_DREGS_H 1 - -/* Forward declaration. */ -enum target_hw_bp_type; - -/* Low-level function vector. */ - -struct i386_dr_low_type - { - /* Set the debug control (DR7) register to a given value for - all LWPs. May be NULL if the debug control register cannot - be set. */ - void (*set_control) (unsigned long); - - /* Put an address into one debug register for all LWPs. May - be NULL if debug registers cannot be set*/ - void (*set_addr) (int, CORE_ADDR); - - /* Return the address in a given debug register of the current - LWP. */ - CORE_ADDR (*get_addr) (int); - - /* Return the value of the debug status (DR6) register for - current LWP. */ - unsigned long (*get_status) (void); - - /* Return the value of the debug control (DR7) register for - current LWP. */ - unsigned long (*get_control) (void); - - /* Number of bytes used for debug registers (4 or 8). */ - int debug_register_length; - }; - -extern struct i386_dr_low_type i386_dr_low; - -/* Debug registers' indices. */ -#define DR_FIRSTADDR 0 -#define DR_LASTADDR 3 -#define DR_NADDR 4 /* The number of debug address registers. */ -#define DR_STATUS 6 /* Index of debug status register (DR6). */ -#define DR_CONTROL 7 /* Index of debug control register (DR7). */ - -/* Global state needed to track h/w watchpoints. */ - -struct i386_debug_reg_state -{ - /* Mirror the inferior's DRi registers. We keep the status and - control registers separated because they don't hold addresses. - Note that since we can change these mirrors while threads are - running, we never trust them to explain a cause of a trap. - For that, we need to peek directly in the inferior registers. */ - CORE_ADDR dr_mirror[DR_NADDR]; - unsigned dr_status_mirror, dr_control_mirror; - - /* Reference counts for each debug register. */ - int dr_ref_count[DR_NADDR]; -}; - -/* A macro to loop over all debug registers. */ -#define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++) - -/* Insert a watchpoint to watch a memory region which starts at - address ADDR and whose length is LEN bytes. Watch memory accesses - of the type TYPE. Return 0 on success, -1 on failure. */ -extern int i386_dr_insert_watchpoint (struct i386_debug_reg_state *state, - enum target_hw_bp_type type, - CORE_ADDR addr, - int len); - -/* Remove a watchpoint that watched the memory region which starts at - address ADDR, whose length is LEN bytes, and for accesses of the - type TYPE. Return 0 on success, -1 on failure. */ -extern int i386_dr_remove_watchpoint (struct i386_debug_reg_state *state, - enum target_hw_bp_type type, - CORE_ADDR addr, - int len); - -/* Return non-zero if we can watch a memory region that starts at - address ADDR and whose length is LEN bytes. */ -extern int i386_dr_region_ok_for_watchpoint (struct i386_debug_reg_state *state, - CORE_ADDR addr, int len); - -/* If the inferior has some break/watchpoint that triggered, set the - address associated with that break/watchpoint and return true. - Otherwise, return false. */ -extern int i386_dr_stopped_data_address (struct i386_debug_reg_state *state, - CORE_ADDR *addr_p); - -/* Return true if the inferior has some watchpoint that triggered. - Otherwise return false. */ -extern int i386_dr_stopped_by_watchpoint (struct i386_debug_reg_state *state); - -#endif /* I386_DREGS_H */ diff --git a/gdb/nat/i386-gcc-cpuid.h b/gdb/nat/i386-gcc-cpuid.h deleted file mode 100644 index 34ab197..0000000 --- a/gdb/nat/i386-gcc-cpuid.h +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Helper cpuid.h file copied from gcc-4.8.0. Code in gdb should not - * include this directly, but pull in i386-cpuid.h and use that func. - */ -/* - * Copyright (C) 2007-2014 Free Software Foundation, Inc. - * - * This file is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 3, or (at your option) any - * later version. - * - * This file is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * Under Section 7 of GPL version 3, you are granted additional - * permissions described in the GCC Runtime Library Exception, version - * 3.1, as published by the Free Software Foundation. - * - * You should have received a copy of the GNU General Public License and - * a copy of the GCC Runtime Library Exception along with this program; - * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - * . - */ - -/* %ecx */ -#define bit_SSE3 (1 << 0) -#define bit_PCLMUL (1 << 1) -#define bit_LZCNT (1 << 5) -#define bit_SSSE3 (1 << 9) -#define bit_FMA (1 << 12) -#define bit_CMPXCHG16B (1 << 13) -#define bit_SSE4_1 (1 << 19) -#define bit_SSE4_2 (1 << 20) -#define bit_MOVBE (1 << 22) -#define bit_POPCNT (1 << 23) -#define bit_AES (1 << 25) -#define bit_XSAVE (1 << 26) -#define bit_OSXSAVE (1 << 27) -#define bit_AVX (1 << 28) -#define bit_F16C (1 << 29) -#define bit_RDRND (1 << 30) - -/* %edx */ -#define bit_CMPXCHG8B (1 << 8) -#define bit_CMOV (1 << 15) -#define bit_MMX (1 << 23) -#define bit_FXSAVE (1 << 24) -#define bit_SSE (1 << 25) -#define bit_SSE2 (1 << 26) - -/* Extended Features */ -/* %ecx */ -#define bit_LAHF_LM (1 << 0) -#define bit_ABM (1 << 5) -#define bit_SSE4a (1 << 6) -#define bit_PRFCHW (1 << 8) -#define bit_XOP (1 << 11) -#define bit_LWP (1 << 15) -#define bit_FMA4 (1 << 16) -#define bit_TBM (1 << 21) - -/* %edx */ -#define bit_MMXEXT (1 << 22) -#define bit_LM (1 << 29) -#define bit_3DNOWP (1 << 30) -#define bit_3DNOW (1 << 31) - -/* Extended Features (%eax == 7) */ -#define bit_FSGSBASE (1 << 0) -#define bit_BMI (1 << 3) -#define bit_HLE (1 << 4) -#define bit_AVX2 (1 << 5) -#define bit_BMI2 (1 << 8) -#define bit_RTM (1 << 11) -#define bit_AVX512F (1 << 16) -#define bit_MPX (1 << 14) -#define bit_RDSEED (1 << 18) -#define bit_ADX (1 << 19) -#define bit_AVX512PF (1 << 26) -#define bit_AVX512ER (1 << 27) -#define bit_AVX512CD (1 << 28) -#define bit_SHA (1 << 29) - -/* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */ -#define bit_XSAVEOPT (1 << 0) - -/* Signatures for different CPU implementations as returned in uses - of cpuid with level 0. */ -#define signature_AMD_ebx 0x68747541 -#define signature_AMD_ecx 0x444d4163 -#define signature_AMD_edx 0x69746e65 - -#define signature_CENTAUR_ebx 0x746e6543 -#define signature_CENTAUR_ecx 0x736c7561 -#define signature_CENTAUR_edx 0x48727561 - -#define signature_CYRIX_ebx 0x69727943 -#define signature_CYRIX_ecx 0x64616574 -#define signature_CYRIX_edx 0x736e4978 - -#define signature_INTEL_ebx 0x756e6547 -#define signature_INTEL_ecx 0x6c65746e -#define signature_INTEL_edx 0x49656e69 - -#define signature_TM1_ebx 0x6e617254 -#define signature_TM1_ecx 0x55504361 -#define signature_TM1_edx 0x74656d73 - -#define signature_TM2_ebx 0x756e6547 -#define signature_TM2_ecx 0x3638784d -#define signature_TM2_edx 0x54656e69 - -#define signature_NSC_ebx 0x646f6547 -#define signature_NSC_ecx 0x43534e20 -#define signature_NSC_edx 0x79622065 - -#define signature_NEXGEN_ebx 0x4778654e -#define signature_NEXGEN_ecx 0x6e657669 -#define signature_NEXGEN_edx 0x72446e65 - -#define signature_RISE_ebx 0x65736952 -#define signature_RISE_ecx 0x65736952 -#define signature_RISE_edx 0x65736952 - -#define signature_SIS_ebx 0x20536953 -#define signature_SIS_ecx 0x20536953 -#define signature_SIS_edx 0x20536953 - -#define signature_UMC_ebx 0x20434d55 -#define signature_UMC_ecx 0x20434d55 -#define signature_UMC_edx 0x20434d55 - -#define signature_VIA_ebx 0x20414956 -#define signature_VIA_ecx 0x20414956 -#define signature_VIA_edx 0x20414956 - -#define signature_VORTEX_ebx 0x74726f56 -#define signature_VORTEX_ecx 0x436f5320 -#define signature_VORTEX_edx 0x36387865 - -#if defined(__i386__) && defined(__PIC__) -/* %ebx may be the PIC register. */ -#if __GNUC__ >= 3 -#define __cpuid(level, a, b, c, d) \ - __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \ - "cpuid\n\t" \ - "xchg{l}\t{%%}ebx, %k1\n\t" \ - : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ - : "0" (level)) - -#define __cpuid_count(level, count, a, b, c, d) \ - __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \ - "cpuid\n\t" \ - "xchg{l}\t{%%}ebx, %k1\n\t" \ - : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ - : "0" (level), "2" (count)) -#else -/* Host GCCs older than 3.0 weren't supporting Intel asm syntax - nor alternatives in i386 code. */ -#define __cpuid(level, a, b, c, d) \ - __asm__ ("xchgl\t%%ebx, %k1\n\t" \ - "cpuid\n\t" \ - "xchgl\t%%ebx, %k1\n\t" \ - : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ - : "0" (level)) - -#define __cpuid_count(level, count, a, b, c, d) \ - __asm__ ("xchgl\t%%ebx, %k1\n\t" \ - "cpuid\n\t" \ - "xchgl\t%%ebx, %k1\n\t" \ - : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ - : "0" (level), "2" (count)) -#endif -#elif defined(__x86_64__) && (defined(__code_model_medium__) || defined(__code_model_large__)) && defined(__PIC__) -/* %rbx may be the PIC register. */ -#define __cpuid(level, a, b, c, d) \ - __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \ - "cpuid\n\t" \ - "xchg{q}\t{%%}rbx, %q1\n\t" \ - : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ - : "0" (level)) - -#define __cpuid_count(level, count, a, b, c, d) \ - __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \ - "cpuid\n\t" \ - "xchg{q}\t{%%}rbx, %q1\n\t" \ - : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ - : "0" (level), "2" (count)) -#else -#define __cpuid(level, a, b, c, d) \ - __asm__ ("cpuid\n\t" \ - : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ - : "0" (level)) - -#define __cpuid_count(level, count, a, b, c, d) \ - __asm__ ("cpuid\n\t" \ - : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ - : "0" (level), "2" (count)) -#endif - -/* Return highest supported input value for cpuid instruction. ext can - be either 0x0 or 0x8000000 to return highest supported value for - basic or extended cpuid information. Function returns 0 if cpuid - is not supported or whatever cpuid returns in eax register. If sig - pointer is non-null, then first four bytes of the signature - (as found in ebx register) are returned in location pointed by sig. */ - -static __inline unsigned int -__get_cpuid_max (unsigned int __ext, unsigned int *__sig) -{ - unsigned int __eax, __ebx, __ecx, __edx; - -#ifndef __x86_64__ - /* See if we can use cpuid. On AMD64 we always can. */ -#if __GNUC__ >= 3 - __asm__ ("pushf{l|d}\n\t" - "pushf{l|d}\n\t" - "pop{l}\t%0\n\t" - "mov{l}\t{%0, %1|%1, %0}\n\t" - "xor{l}\t{%2, %0|%0, %2}\n\t" - "push{l}\t%0\n\t" - "popf{l|d}\n\t" - "pushf{l|d}\n\t" - "pop{l}\t%0\n\t" - "popf{l|d}\n\t" - : "=&r" (__eax), "=&r" (__ebx) - : "i" (0x00200000)); -#else -/* Host GCCs older than 3.0 weren't supporting Intel asm syntax - nor alternatives in i386 code. */ - __asm__ ("pushfl\n\t" - "pushfl\n\t" - "popl\t%0\n\t" - "movl\t%0, %1\n\t" - "xorl\t%2, %0\n\t" - "pushl\t%0\n\t" - "popfl\n\t" - "pushfl\n\t" - "popl\t%0\n\t" - "popfl\n\t" - : "=&r" (__eax), "=&r" (__ebx) - : "i" (0x00200000)); -#endif - - if (!((__eax ^ __ebx) & 0x00200000)) - return 0; -#endif - - /* Host supports cpuid. Return highest supported cpuid input value. */ - __cpuid (__ext, __eax, __ebx, __ecx, __edx); - - if (__sig) - *__sig = __ebx; - - return __eax; -} - -/* Return cpuid data for requested cpuid level, as found in returned - eax, ebx, ecx and edx registers. The function checks if cpuid is - supported and returns 1 for valid cpuid information or 0 for - unsupported cpuid level. All pointers are required to be non-null. */ - -static __inline int -__get_cpuid (unsigned int __level, - unsigned int *__eax, unsigned int *__ebx, - unsigned int *__ecx, unsigned int *__edx) -{ - unsigned int __ext = __level & 0x80000000; - - if (__get_cpuid_max (__ext, 0) < __level) - return 0; - - __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx); - return 1; -} diff --git a/gdb/nat/linux-btrace.c b/gdb/nat/linux-btrace.c index f6fdbda..e0106fa 100644 --- a/gdb/nat/linux-btrace.c +++ b/gdb/nat/linux-btrace.c @@ -29,7 +29,7 @@ #include "regcache.h" #include "gdbthread.h" #include "gdb_wait.h" -#include "i386-cpuid.h" +#include "x86-cpuid.h" #ifdef HAVE_SYS_SYSCALL_H #include @@ -348,7 +348,7 @@ intel_supports_btrace (void) { unsigned int cpuid, model, family; - if (!i386_cpuid (1, &cpuid, NULL, NULL, NULL)) + if (!x86_cpuid (1, &cpuid, NULL, NULL, NULL)) return 0; family = (cpuid >> 8) & 0xf; @@ -389,7 +389,7 @@ cpu_supports_btrace (void) { unsigned int ebx, ecx, edx; - if (!i386_cpuid (0, NULL, &ebx, &ecx, &edx)) + if (!x86_cpuid (0, NULL, &ebx, &ecx, &edx)) return 0; if (ebx == signature_INTEL_ebx && ecx == signature_INTEL_ecx diff --git a/gdb/nat/x86-cpuid.h b/gdb/nat/x86-cpuid.h new file mode 100644 index 0000000..3e4a481 --- /dev/null +++ b/gdb/nat/x86-cpuid.h @@ -0,0 +1,63 @@ +/* C API for x86 cpuid insn. + Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GDB. + + This file is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 3, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifndef X86_CPUID_COMMON_H +#define X86_CPUID_COMMON_H + +/* Always include the header for the cpu bit defines. */ +#include "x86-gcc-cpuid.h" + +#if defined(__i386__) || defined(__x86_64__) + +/* Return cpuid data for requested cpuid level, as found in returned + eax, ebx, ecx and edx registers. The function checks if cpuid is + supported and returns 1 for valid cpuid information or 0 for + unsupported cpuid level. Pointers may be non-null. */ + +static __inline int +x86_cpuid (unsigned int __level, + unsigned int *__eax, unsigned int *__ebx, + unsigned int *__ecx, unsigned int *__edx) +{ + unsigned int __scratch; + + if (!__eax) + __eax = &__scratch; + if (!__ebx) + __ebx = &__scratch; + if (!__ecx) + __ecx = &__scratch; + if (!__edx) + __edx = &__scratch; + + return __get_cpuid (__level, __eax, __ebx, __ecx, __edx); +} + +#else + +static __inline int +x86_cpuid (unsigned int __level, + unsigned int *__eax, unsigned int *__ebx, + unsigned int *__ecx, unsigned int *__edx) +{ + return 0; +} + +#endif /* i386 && x86_64 */ + +#endif /* X86_CPUID_COMMON_H */ diff --git a/gdb/nat/x86-dregs.c b/gdb/nat/x86-dregs.c new file mode 100644 index 0000000..5381c77 --- /dev/null +++ b/gdb/nat/x86-dregs.c @@ -0,0 +1,664 @@ +/* Debug register code for x86 (i386 and x86-64). + + Copyright (C) 2001-2014 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#ifdef GDBSERVER +#include "server.h" +#else +#include "defs.h" +#include "inferior.h" +#endif +#include "x86-dregs.h" + +/* Support for hardware watchpoints and breakpoints using the x86 + debug registers. + + This provides several functions for inserting and removing + hardware-assisted breakpoints and watchpoints, testing if one or + more of the watchpoints triggered and at what address, checking + whether a given region can be watched, etc. + + The functions below implement debug registers sharing by reference + counts, and allow to watch regions up to 16 bytes long. */ + +/* Accessor macros for low-level function vector. */ + +/* Can we update the inferior's debug registers? */ +#define x86_dr_low_can_set_addr() (x86_dr_low.set_addr != NULL) + +/* Update the inferior's debug register REGNUM from STATE. */ +#define x86_dr_low_set_addr(new_state, i) \ + (x86_dr_low.set_addr ((i), (new_state)->dr_mirror[(i)])) + +/* Return the inferior's debug register REGNUM. */ +#define x86_dr_low_get_addr(i) (x86_dr_low.get_addr ((i))) + +/* Can we update the inferior's DR7 control register? */ +#define x86_dr_low_can_set_control() (x86_dr_low.set_control != NULL) + +/* Update the inferior's DR7 debug control register from STATE. */ +#define x86_dr_low_set_control(new_state) \ + (x86_dr_low.set_control ((new_state)->dr_control_mirror)) + +/* Return the value of the inferior's DR7 debug control register. */ +#define x86_dr_low_get_control() (x86_dr_low.get_control ()) + +/* Return the value of the inferior's DR6 debug status register. */ +#define x86_dr_low_get_status() (x86_dr_low.get_status ()) + +/* Return the debug register size, in bytes. */ +#define x86_get_debug_register_length() \ + (x86_dr_low.debug_register_length) + +/* Support for 8-byte wide hw watchpoints. */ +#define TARGET_HAS_DR_LEN_8 (x86_get_debug_register_length () == 8) + +/* DR7 Debug Control register fields. */ + +/* How many bits to skip in DR7 to get to R/W and LEN fields. */ +#define DR_CONTROL_SHIFT 16 +/* How many bits in DR7 per R/W and LEN field for each watchpoint. */ +#define DR_CONTROL_SIZE 4 + +/* Watchpoint/breakpoint read/write fields in DR7. */ +#define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ +#define DR_RW_WRITE (0x1) /* Break on data writes. */ +#define DR_RW_READ (0x3) /* Break on data reads or writes. */ + +/* This is here for completeness. No platform supports this + functionality yet (as of March 2001). Note that the DE flag in the + CR4 register needs to be set to support this. */ +#ifndef DR_RW_IORW +#define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ +#endif + +/* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift + is so we could OR this with the read/write field defined above. */ +#define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ +#define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ +#define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ +#define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ + +/* Local and Global Enable flags in DR7. + + When the Local Enable flag is set, the breakpoint/watchpoint is + enabled only for the current task; the processor automatically + clears this flag on every task switch. When the Global Enable flag + is set, the breakpoint/watchpoint is enabled for all tasks; the + processor never clears this flag. + + Currently, all watchpoint are locally enabled. If you need to + enable them globally, read the comment which pertains to this in + x86_insert_aligned_watchpoint below. */ +#define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ +#define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ +#define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ + +/* Local and global exact breakpoint enable flags (a.k.a. slowdown + flags). These are only required on i386, to allow detection of the + exact instruction which caused a watchpoint to break; i486 and + later processors do that automatically. We set these flags for + backwards compatibility. */ +#define DR_LOCAL_SLOWDOWN (0x100) +#define DR_GLOBAL_SLOWDOWN (0x200) + +/* Fields reserved by Intel. This includes the GD (General Detect + Enable) flag, which causes a debug exception to be generated when a + MOV instruction accesses one of the debug registers. + + FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ +#define DR_CONTROL_RESERVED (0xFC00) + +/* Auxiliary helper macros. */ + +/* A value that masks all fields in DR7 that are reserved by Intel. */ +#define X86_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) + +/* The I'th debug register is vacant if its Local and Global Enable + bits are reset in the Debug Control register. */ +#define X86_DR_VACANT(state, i) \ + (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) + +/* Locally enable the break/watchpoint in the I'th debug register. */ +#define X86_DR_LOCAL_ENABLE(state, i) \ + do { \ + (state)->dr_control_mirror |= \ + (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ + } while (0) + +/* Globally enable the break/watchpoint in the I'th debug register. */ +#define X86_DR_GLOBAL_ENABLE(state, i) \ + do { \ + (state)->dr_control_mirror |= \ + (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ + } while (0) + +/* Disable the break/watchpoint in the I'th debug register. */ +#define X86_DR_DISABLE(state, i) \ + do { \ + (state)->dr_control_mirror &= \ + ~(3 << (DR_ENABLE_SIZE * (i))); \ + } while (0) + +/* Set in DR7 the RW and LEN fields for the I'th debug register. */ +#define X86_DR_SET_RW_LEN(state, i, rwlen) \ + do { \ + (state)->dr_control_mirror &= \ + ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ + (state)->dr_control_mirror |= \ + ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ + } while (0) + +/* Get from DR7 the RW and LEN fields for the I'th debug register. */ +#define X86_DR_GET_RW_LEN(dr7, i) \ + (((dr7) \ + >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) + +/* Did the watchpoint whose address is in the I'th register break? */ +#define X86_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i))) + +/* Types of operations supported by x86_handle_nonaligned_watchpoint. */ +typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } x86_wp_op_t; + +#ifndef GDBSERVER +/* Whether or not to print the mirrored debug registers. */ +extern int debug_hw_points; +#endif + +/* Print the values of the mirrored debug registers. */ + +static void +x86_show_dr (struct x86_debug_reg_state *state, + const char *func, CORE_ADDR addr, + int len, enum target_hw_bp_type type) +{ + int i; + + debug_printf ("%s", func); + if (addr || len) + debug_printf (" (addr=%s, len=%d, type=%s)", + phex (addr, 8), len, + type == hw_write ? "data-write" + : (type == hw_read ? "data-read" + : (type == hw_access ? "data-read/write" + : (type == hw_execute ? "instruction-execute" + /* FIXME: if/when I/O read/write + watchpoints are supported, add them + here. */ + : "??unknown??")))); + debug_printf (":\n"); + debug_printf ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", + phex (state->dr_control_mirror, 8), + phex (state->dr_status_mirror, 8)); + ALL_DEBUG_REGISTERS (i) + { + debug_printf ("\ +\tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", + i, phex (state->dr_mirror[i], + x86_get_debug_register_length ()), + state->dr_ref_count[i], + i + 1, phex (state->dr_mirror[i + 1], + x86_get_debug_register_length ()), + state->dr_ref_count[i + 1]); + i++; + } +} + +/* Return the value of a 4-bit field for DR7 suitable for watching a + region of LEN bytes for accesses of type TYPE. LEN is assumed to + have the value of 1, 2, or 4. */ + +static unsigned +x86_length_and_rw_bits (int len, enum target_hw_bp_type type) +{ + unsigned rw; + + switch (type) + { + case hw_execute: + rw = DR_RW_EXECUTE; + break; + case hw_write: + rw = DR_RW_WRITE; + break; + case hw_read: + internal_error (__FILE__, __LINE__, + _("The i386 doesn't support " + "data-read watchpoints.\n")); + case hw_access: + rw = DR_RW_READ; + break; +#if 0 + /* Not yet supported. */ + case hw_io_access: + rw = DR_RW_IORW; + break; +#endif + default: + internal_error (__FILE__, __LINE__, _("\ +Invalid hardware breakpoint type %d in x86_length_and_rw_bits.\n"), + (int) type); + } + + switch (len) + { + case 1: + return (DR_LEN_1 | rw); + case 2: + return (DR_LEN_2 | rw); + case 4: + return (DR_LEN_4 | rw); + case 8: + if (TARGET_HAS_DR_LEN_8) + return (DR_LEN_8 | rw); + /* ELSE FALL THROUGH */ + default: + internal_error (__FILE__, __LINE__, _("\ +Invalid hardware breakpoint length %d in x86_length_and_rw_bits.\n"), len); + } +} + +/* Insert a watchpoint at address ADDR, which is assumed to be aligned + according to the length of the region to watch. LEN_RW_BITS is the + value of the bits from DR7 which describes the length and access + type of the region to be watched by this watchpoint. Return 0 on + success, -1 on failure. */ + +static int +x86_insert_aligned_watchpoint (struct x86_debug_reg_state *state, + CORE_ADDR addr, unsigned len_rw_bits) +{ + int i; + + if (!x86_dr_low_can_set_addr () || !x86_dr_low_can_set_control ()) + return -1; + + /* First, look for an occupied debug register with the same address + and the same RW and LEN definitions. If we find one, we can + reuse it for this watchpoint as well (and save a register). */ + ALL_DEBUG_REGISTERS (i) + { + if (!X86_DR_VACANT (state, i) + && state->dr_mirror[i] == addr + && X86_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) + { + state->dr_ref_count[i]++; + return 0; + } + } + + /* Next, look for a vacant debug register. */ + ALL_DEBUG_REGISTERS (i) + { + if (X86_DR_VACANT (state, i)) + break; + } + + /* No more debug registers! */ + if (i >= DR_NADDR) + return -1; + + /* Now set up the register I to watch our region. */ + + /* Record the info in our local mirrored array. */ + state->dr_mirror[i] = addr; + state->dr_ref_count[i] = 1; + X86_DR_SET_RW_LEN (state, i, len_rw_bits); + /* Note: we only enable the watchpoint locally, i.e. in the current + task. Currently, no x86 target allows or supports global + watchpoints; however, if any target would want that in the + future, GDB should probably provide a command to control whether + to enable watchpoints globally or locally, and the code below + should use global or local enable and slow-down flags as + appropriate. */ + X86_DR_LOCAL_ENABLE (state, i); + state->dr_control_mirror |= DR_LOCAL_SLOWDOWN; + state->dr_control_mirror &= X86_DR_CONTROL_MASK; + + return 0; +} + +/* Remove a watchpoint at address ADDR, which is assumed to be aligned + according to the length of the region to watch. LEN_RW_BITS is the + value of the bits from DR7 which describes the length and access + type of the region watched by this watchpoint. Return 0 on + success, -1 on failure. */ + +static int +x86_remove_aligned_watchpoint (struct x86_debug_reg_state *state, + CORE_ADDR addr, unsigned len_rw_bits) +{ + int i, retval = -1; + int all_vacant = 1; + + ALL_DEBUG_REGISTERS (i) + { + if (!X86_DR_VACANT (state, i) + && state->dr_mirror[i] == addr + && X86_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) + { + if (--state->dr_ref_count[i] == 0) /* No longer in use? */ + { + /* Reset our mirror. */ + state->dr_mirror[i] = 0; + X86_DR_DISABLE (state, i); + /* Even though not strictly necessary, clear out all + bits in DR_CONTROL related to this debug register. + Debug output is clearer when we don't have stale bits + in place. This also allows the assertion below. */ + X86_DR_SET_RW_LEN (state, i, 0); + } + retval = 0; + } + + if (!X86_DR_VACANT (state, i)) + all_vacant = 0; + } + + if (all_vacant) + { + /* Even though not strictly necessary, clear out all of + DR_CONTROL, so that when we have no debug registers in use, + we end up with DR_CONTROL == 0. The Linux support relies on + this for an optimization. Plus, it makes for clearer debug + output. */ + state->dr_control_mirror &= ~DR_LOCAL_SLOWDOWN; + + gdb_assert (state->dr_control_mirror == 0); + } + return retval; +} + +/* Insert or remove a (possibly non-aligned) watchpoint, or count the + number of debug registers required to watch a region at address + ADDR whose length is LEN for accesses of type TYPE. Return 0 on + successful insertion or removal, a positive number when queried + about the number of registers, or -1 on failure. If WHAT is not a + valid value, bombs through internal_error. */ + +static int +x86_handle_nonaligned_watchpoint (struct x86_debug_reg_state *state, + x86_wp_op_t what, CORE_ADDR addr, int len, + enum target_hw_bp_type type) +{ + int retval = 0; + int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; + + static const int size_try_array[8][8] = + { + {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ + {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ + {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ + {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ + {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ + {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ + {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ + {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ + }; + + while (len > 0) + { + int align = addr % max_wp_len; + /* Four (eight on AMD64) is the maximum length a debug register + can watch. */ + int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); + int size = size_try_array[try][align]; + + if (what == WP_COUNT) + { + /* size_try_array[] is defined such that each iteration + through the loop is guaranteed to produce an address and a + size that can be watched with a single debug register. + Thus, for counting the registers required to watch a + region, we simply need to increment the count on each + iteration. */ + retval++; + } + else + { + unsigned len_rw = x86_length_and_rw_bits (size, type); + + if (what == WP_INSERT) + retval = x86_insert_aligned_watchpoint (state, addr, len_rw); + else if (what == WP_REMOVE) + retval = x86_remove_aligned_watchpoint (state, addr, len_rw); + else + internal_error (__FILE__, __LINE__, _("\ +Invalid value %d of operation in x86_handle_nonaligned_watchpoint.\n"), + (int) what); + if (retval) + break; + } + + addr += size; + len -= size; + } + + return retval; +} + +/* Update the inferior debug registers state, in STATE, with the + new debug registers state, in NEW_STATE. */ + +static void +x86_update_inferior_debug_regs (struct x86_debug_reg_state *state, + struct x86_debug_reg_state *new_state) +{ + int i; + + ALL_DEBUG_REGISTERS (i) + { + if (X86_DR_VACANT (new_state, i) != X86_DR_VACANT (state, i)) + x86_dr_low_set_addr (new_state, i); + else + gdb_assert (new_state->dr_mirror[i] == state->dr_mirror[i]); + } + + if (new_state->dr_control_mirror != state->dr_control_mirror) + x86_dr_low_set_control (new_state); + + *state = *new_state; +} + +/* Insert a watchpoint to watch a memory region which starts at + address ADDR and whose length is LEN bytes. Watch memory accesses + of the type TYPE. Return 0 on success, -1 on failure. */ + +int +x86_dr_insert_watchpoint (struct x86_debug_reg_state *state, + enum target_hw_bp_type type, + CORE_ADDR addr, int len) +{ + int retval; + /* Work on a local copy of the debug registers, and on success, + commit the change back to the inferior. */ + struct x86_debug_reg_state local_state = *state; + + if (type == hw_read) + return 1; /* unsupported */ + + if (((len != 1 && len != 2 && len != 4) + && !(TARGET_HAS_DR_LEN_8 && len == 8)) + || addr % len != 0) + { + retval = x86_handle_nonaligned_watchpoint (&local_state, + WP_INSERT, + addr, len, type); + } + else + { + unsigned len_rw = x86_length_and_rw_bits (len, type); + + retval = x86_insert_aligned_watchpoint (&local_state, + addr, len_rw); + } + + if (retval == 0) + x86_update_inferior_debug_regs (state, &local_state); + + if (debug_hw_points) + x86_show_dr (state, "insert_watchpoint", addr, len, type); + + return retval; +} + +/* Remove a watchpoint that watched the memory region which starts at + address ADDR, whose length is LEN bytes, and for accesses of the + type TYPE. Return 0 on success, -1 on failure. */ + +int +x86_dr_remove_watchpoint (struct x86_debug_reg_state *state, + enum target_hw_bp_type type, + CORE_ADDR addr, int len) +{ + int retval; + /* Work on a local copy of the debug registers, and on success, + commit the change back to the inferior. */ + struct x86_debug_reg_state local_state = *state; + + if (((len != 1 && len != 2 && len != 4) + && !(TARGET_HAS_DR_LEN_8 && len == 8)) + || addr % len != 0) + { + retval = x86_handle_nonaligned_watchpoint (&local_state, + WP_REMOVE, + addr, len, type); + } + else + { + unsigned len_rw = x86_length_and_rw_bits (len, type); + + retval = x86_remove_aligned_watchpoint (&local_state, + addr, len_rw); + } + + if (retval == 0) + x86_update_inferior_debug_regs (state, &local_state); + + if (debug_hw_points) + x86_show_dr (state, "remove_watchpoint", addr, len, type); + + return retval; +} + +/* Return non-zero if we can watch a memory region that starts at + address ADDR and whose length is LEN bytes. */ + +int +x86_dr_region_ok_for_watchpoint (struct x86_debug_reg_state *state, + CORE_ADDR addr, int len) +{ + int nregs; + + /* Compute how many aligned watchpoints we would need to cover this + region. */ + nregs = x86_handle_nonaligned_watchpoint (state, WP_COUNT, + addr, len, hw_write); + return nregs <= DR_NADDR ? 1 : 0; +} + +/* If the inferior has some break/watchpoint that triggered, set the + address associated with that break/watchpoint and return non-zero. + Otherwise, return zero. */ + +int +x86_dr_stopped_data_address (struct x86_debug_reg_state *state, + CORE_ADDR *addr_p) +{ + CORE_ADDR addr = 0; + int i; + int rc = 0; + /* The current thread's DR_STATUS. We always need to read this to + check whether some watchpoint caused the trap. */ + unsigned status; + /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a + data breakpoint trap. Only fetch it when necessary, to avoid an + unnecessary extra syscall when no watchpoint triggered. */ + int control_p = 0; + unsigned control = 0; + + /* In non-stop/async, threads can be running while we change the + global dr_mirror (and friends). Say, we set a watchpoint, and + let threads resume. Now, say you delete the watchpoint, or + add/remove watchpoints such that dr_mirror changes while threads + are running. On targets that support non-stop, + inserting/deleting watchpoints updates the global dr_mirror only. + It does not update the real thread's debug registers; that's only + done prior to resume. Instead, if threads are running when the + mirror changes, a temporary and transparent stop on all threads + is forced so they can get their copy of the debug registers + updated on re-resume. Now, say, a thread hit a watchpoint before + having been updated with the new dr_mirror contents, and we + haven't yet handled the corresponding SIGTRAP. If we trusted + dr_mirror below, we'd mistake the real trapped address (from the + last time we had updated debug registers in the thread) with + whatever was currently in dr_mirror. So to fix this, dr_mirror + always represents intention, what we _want_ threads to have in + debug registers. To get at the address and cause of the trap, we + need to read the state the thread still has in its debug + registers. + + In sum, always get the current debug register values the current + thread has, instead of trusting the global mirror. If the thread + was running when we last changed watchpoints, the mirror no + longer represents what was set in this thread's debug + registers. */ + status = x86_dr_low_get_status (); + + ALL_DEBUG_REGISTERS (i) + { + if (!X86_DR_WATCH_HIT (status, i)) + continue; + + if (!control_p) + { + control = x86_dr_low_get_control (); + control_p = 1; + } + + /* This second condition makes sure DRi is set up for a data + watchpoint, not a hardware breakpoint. The reason is that + GDB doesn't call the target_stopped_data_address method + except for data watchpoints. In other words, I'm being + paranoiac. */ + if (X86_DR_GET_RW_LEN (control, i) != 0) + { + addr = x86_dr_low_get_addr (i); + rc = 1; + if (debug_hw_points) + x86_show_dr (state, "watchpoint_hit", addr, -1, hw_write); + } + } + + if (debug_hw_points && addr == 0) + x86_show_dr (state, "stopped_data_addr", 0, 0, hw_write); + + if (rc) + *addr_p = addr; + return rc; +} + +/* Return non-zero if the inferior has some watchpoint that triggered. + Otherwise return zero. */ + +int +x86_dr_stopped_by_watchpoint (struct x86_debug_reg_state *state) +{ + CORE_ADDR addr = 0; + return x86_dr_stopped_data_address (state, &addr); +} diff --git a/gdb/nat/x86-dregs.h b/gdb/nat/x86-dregs.h new file mode 100644 index 0000000..fb179a5 --- /dev/null +++ b/gdb/nat/x86-dregs.h @@ -0,0 +1,126 @@ +/* Debug register code for x86 (i386 and x86-64). + + Copyright (C) 2009-2014 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +/* Support for hardware watchpoints and breakpoints using the x86 + debug registers. + + This provides several functions for inserting and removing + hardware-assisted breakpoints and watchpoints, testing if one or + more of the watchpoints triggered and at what address, checking + whether a given region can be watched, etc. + + The functions below implement debug registers sharing by reference + counts, and allow to watch regions up to 16 bytes long + (32 bytes on 64 bit hosts). */ + +#ifndef X86_DREGS_H +#define X86_DREGS_H 1 + +/* Forward declaration. */ +enum target_hw_bp_type; + +/* Low-level function vector. */ + +struct x86_dr_low_type + { + /* Set the debug control (DR7) register to a given value for + all LWPs. May be NULL if the debug control register cannot + be set. */ + void (*set_control) (unsigned long); + + /* Put an address into one debug register for all LWPs. May + be NULL if debug registers cannot be set*/ + void (*set_addr) (int, CORE_ADDR); + + /* Return the address in a given debug register of the current + LWP. */ + CORE_ADDR (*get_addr) (int); + + /* Return the value of the debug status (DR6) register for + current LWP. */ + unsigned long (*get_status) (void); + + /* Return the value of the debug control (DR7) register for + current LWP. */ + unsigned long (*get_control) (void); + + /* Number of bytes used for debug registers (4 or 8). */ + int debug_register_length; + }; + +extern struct x86_dr_low_type x86_dr_low; + +/* Debug registers' indices. */ +#define DR_FIRSTADDR 0 +#define DR_LASTADDR 3 +#define DR_NADDR 4 /* The number of debug address registers. */ +#define DR_STATUS 6 /* Index of debug status register (DR6). */ +#define DR_CONTROL 7 /* Index of debug control register (DR7). */ + +/* Global state needed to track h/w watchpoints. */ + +struct x86_debug_reg_state +{ + /* Mirror the inferior's DRi registers. We keep the status and + control registers separated because they don't hold addresses. + Note that since we can change these mirrors while threads are + running, we never trust them to explain a cause of a trap. + For that, we need to peek directly in the inferior registers. */ + CORE_ADDR dr_mirror[DR_NADDR]; + unsigned dr_status_mirror, dr_control_mirror; + + /* Reference counts for each debug register. */ + int dr_ref_count[DR_NADDR]; +}; + +/* A macro to loop over all debug registers. */ +#define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++) + +/* Insert a watchpoint to watch a memory region which starts at + address ADDR and whose length is LEN bytes. Watch memory accesses + of the type TYPE. Return 0 on success, -1 on failure. */ +extern int x86_dr_insert_watchpoint (struct x86_debug_reg_state *state, + enum target_hw_bp_type type, + CORE_ADDR addr, + int len); + +/* Remove a watchpoint that watched the memory region which starts at + address ADDR, whose length is LEN bytes, and for accesses of the + type TYPE. Return 0 on success, -1 on failure. */ +extern int x86_dr_remove_watchpoint (struct x86_debug_reg_state *state, + enum target_hw_bp_type type, + CORE_ADDR addr, + int len); + +/* Return non-zero if we can watch a memory region that starts at + address ADDR and whose length is LEN bytes. */ +extern int x86_dr_region_ok_for_watchpoint (struct x86_debug_reg_state *state, + CORE_ADDR addr, int len); + +/* If the inferior has some break/watchpoint that triggered, set the + address associated with that break/watchpoint and return true. + Otherwise, return false. */ +extern int x86_dr_stopped_data_address (struct x86_debug_reg_state *state, + CORE_ADDR *addr_p); + +/* Return true if the inferior has some watchpoint that triggered. + Otherwise return false. */ +extern int x86_dr_stopped_by_watchpoint (struct x86_debug_reg_state *state); + +#endif /* X86_DREGS_H */ diff --git a/gdb/nat/x86-gcc-cpuid.h b/gdb/nat/x86-gcc-cpuid.h new file mode 100644 index 0000000..18763ad --- /dev/null +++ b/gdb/nat/x86-gcc-cpuid.h @@ -0,0 +1,278 @@ +/* + * Helper cpuid.h file copied from gcc-4.8.0. Code in gdb should not + * include this directly, but pull in x86-cpuid.h and use that func. + */ +/* + * Copyright (C) 2007-2014 Free Software Foundation, Inc. + * + * This file is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 3, or (at your option) any + * later version. + * + * This file is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * Under Section 7 of GPL version 3, you are granted additional + * permissions described in the GCC Runtime Library Exception, version + * 3.1, as published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License and + * a copy of the GCC Runtime Library Exception along with this program; + * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + * . + */ + +/* %ecx */ +#define bit_SSE3 (1 << 0) +#define bit_PCLMUL (1 << 1) +#define bit_LZCNT (1 << 5) +#define bit_SSSE3 (1 << 9) +#define bit_FMA (1 << 12) +#define bit_CMPXCHG16B (1 << 13) +#define bit_SSE4_1 (1 << 19) +#define bit_SSE4_2 (1 << 20) +#define bit_MOVBE (1 << 22) +#define bit_POPCNT (1 << 23) +#define bit_AES (1 << 25) +#define bit_XSAVE (1 << 26) +#define bit_OSXSAVE (1 << 27) +#define bit_AVX (1 << 28) +#define bit_F16C (1 << 29) +#define bit_RDRND (1 << 30) + +/* %edx */ +#define bit_CMPXCHG8B (1 << 8) +#define bit_CMOV (1 << 15) +#define bit_MMX (1 << 23) +#define bit_FXSAVE (1 << 24) +#define bit_SSE (1 << 25) +#define bit_SSE2 (1 << 26) + +/* Extended Features */ +/* %ecx */ +#define bit_LAHF_LM (1 << 0) +#define bit_ABM (1 << 5) +#define bit_SSE4a (1 << 6) +#define bit_PRFCHW (1 << 8) +#define bit_XOP (1 << 11) +#define bit_LWP (1 << 15) +#define bit_FMA4 (1 << 16) +#define bit_TBM (1 << 21) + +/* %edx */ +#define bit_MMXEXT (1 << 22) +#define bit_LM (1 << 29) +#define bit_3DNOWP (1 << 30) +#define bit_3DNOW (1 << 31) + +/* Extended Features (%eax == 7) */ +#define bit_FSGSBASE (1 << 0) +#define bit_BMI (1 << 3) +#define bit_HLE (1 << 4) +#define bit_AVX2 (1 << 5) +#define bit_BMI2 (1 << 8) +#define bit_RTM (1 << 11) +#define bit_AVX512F (1 << 16) +#define bit_MPX (1 << 14) +#define bit_RDSEED (1 << 18) +#define bit_ADX (1 << 19) +#define bit_AVX512PF (1 << 26) +#define bit_AVX512ER (1 << 27) +#define bit_AVX512CD (1 << 28) +#define bit_SHA (1 << 29) + +/* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */ +#define bit_XSAVEOPT (1 << 0) + +/* Signatures for different CPU implementations as returned in uses + of cpuid with level 0. */ +#define signature_AMD_ebx 0x68747541 +#define signature_AMD_ecx 0x444d4163 +#define signature_AMD_edx 0x69746e65 + +#define signature_CENTAUR_ebx 0x746e6543 +#define signature_CENTAUR_ecx 0x736c7561 +#define signature_CENTAUR_edx 0x48727561 + +#define signature_CYRIX_ebx 0x69727943 +#define signature_CYRIX_ecx 0x64616574 +#define signature_CYRIX_edx 0x736e4978 + +#define signature_INTEL_ebx 0x756e6547 +#define signature_INTEL_ecx 0x6c65746e +#define signature_INTEL_edx 0x49656e69 + +#define signature_TM1_ebx 0x6e617254 +#define signature_TM1_ecx 0x55504361 +#define signature_TM1_edx 0x74656d73 + +#define signature_TM2_ebx 0x756e6547 +#define signature_TM2_ecx 0x3638784d +#define signature_TM2_edx 0x54656e69 + +#define signature_NSC_ebx 0x646f6547 +#define signature_NSC_ecx 0x43534e20 +#define signature_NSC_edx 0x79622065 + +#define signature_NEXGEN_ebx 0x4778654e +#define signature_NEXGEN_ecx 0x6e657669 +#define signature_NEXGEN_edx 0x72446e65 + +#define signature_RISE_ebx 0x65736952 +#define signature_RISE_ecx 0x65736952 +#define signature_RISE_edx 0x65736952 + +#define signature_SIS_ebx 0x20536953 +#define signature_SIS_ecx 0x20536953 +#define signature_SIS_edx 0x20536953 + +#define signature_UMC_ebx 0x20434d55 +#define signature_UMC_ecx 0x20434d55 +#define signature_UMC_edx 0x20434d55 + +#define signature_VIA_ebx 0x20414956 +#define signature_VIA_ecx 0x20414956 +#define signature_VIA_edx 0x20414956 + +#define signature_VORTEX_ebx 0x74726f56 +#define signature_VORTEX_ecx 0x436f5320 +#define signature_VORTEX_edx 0x36387865 + +#if defined(__i386__) && defined(__PIC__) +/* %ebx may be the PIC register. */ +#if __GNUC__ >= 3 +#define __cpuid(level, a, b, c, d) \ + __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \ + "cpuid\n\t" \ + "xchg{l}\t{%%}ebx, %k1\n\t" \ + : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ + : "0" (level)) + +#define __cpuid_count(level, count, a, b, c, d) \ + __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \ + "cpuid\n\t" \ + "xchg{l}\t{%%}ebx, %k1\n\t" \ + : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ + : "0" (level), "2" (count)) +#else +/* Host GCCs older than 3.0 weren't supporting Intel asm syntax + nor alternatives in i386 code. */ +#define __cpuid(level, a, b, c, d) \ + __asm__ ("xchgl\t%%ebx, %k1\n\t" \ + "cpuid\n\t" \ + "xchgl\t%%ebx, %k1\n\t" \ + : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ + : "0" (level)) + +#define __cpuid_count(level, count, a, b, c, d) \ + __asm__ ("xchgl\t%%ebx, %k1\n\t" \ + "cpuid\n\t" \ + "xchgl\t%%ebx, %k1\n\t" \ + : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ + : "0" (level), "2" (count)) +#endif +#elif defined(__x86_64__) && (defined(__code_model_medium__) || defined(__code_model_large__)) && defined(__PIC__) +/* %rbx may be the PIC register. */ +#define __cpuid(level, a, b, c, d) \ + __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \ + "cpuid\n\t" \ + "xchg{q}\t{%%}rbx, %q1\n\t" \ + : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ + : "0" (level)) + +#define __cpuid_count(level, count, a, b, c, d) \ + __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \ + "cpuid\n\t" \ + "xchg{q}\t{%%}rbx, %q1\n\t" \ + : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ + : "0" (level), "2" (count)) +#else +#define __cpuid(level, a, b, c, d) \ + __asm__ ("cpuid\n\t" \ + : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ + : "0" (level)) + +#define __cpuid_count(level, count, a, b, c, d) \ + __asm__ ("cpuid\n\t" \ + : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ + : "0" (level), "2" (count)) +#endif + +/* Return highest supported input value for cpuid instruction. ext can + be either 0x0 or 0x8000000 to return highest supported value for + basic or extended cpuid information. Function returns 0 if cpuid + is not supported or whatever cpuid returns in eax register. If sig + pointer is non-null, then first four bytes of the signature + (as found in ebx register) are returned in location pointed by sig. */ + +static __inline unsigned int +__get_cpuid_max (unsigned int __ext, unsigned int *__sig) +{ + unsigned int __eax, __ebx, __ecx, __edx; + +#ifndef __x86_64__ + /* See if we can use cpuid. On AMD64 we always can. */ +#if __GNUC__ >= 3 + __asm__ ("pushf{l|d}\n\t" + "pushf{l|d}\n\t" + "pop{l}\t%0\n\t" + "mov{l}\t{%0, %1|%1, %0}\n\t" + "xor{l}\t{%2, %0|%0, %2}\n\t" + "push{l}\t%0\n\t" + "popf{l|d}\n\t" + "pushf{l|d}\n\t" + "pop{l}\t%0\n\t" + "popf{l|d}\n\t" + : "=&r" (__eax), "=&r" (__ebx) + : "i" (0x00200000)); +#else +/* Host GCCs older than 3.0 weren't supporting Intel asm syntax + nor alternatives in i386 code. */ + __asm__ ("pushfl\n\t" + "pushfl\n\t" + "popl\t%0\n\t" + "movl\t%0, %1\n\t" + "xorl\t%2, %0\n\t" + "pushl\t%0\n\t" + "popfl\n\t" + "pushfl\n\t" + "popl\t%0\n\t" + "popfl\n\t" + : "=&r" (__eax), "=&r" (__ebx) + : "i" (0x00200000)); +#endif + + if (!((__eax ^ __ebx) & 0x00200000)) + return 0; +#endif + + /* Host supports cpuid. Return highest supported cpuid input value. */ + __cpuid (__ext, __eax, __ebx, __ecx, __edx); + + if (__sig) + *__sig = __ebx; + + return __eax; +} + +/* Return cpuid data for requested cpuid level, as found in returned + eax, ebx, ecx and edx registers. The function checks if cpuid is + supported and returns 1 for valid cpuid information or 0 for + unsupported cpuid level. All pointers are required to be non-null. */ + +static __inline int +__get_cpuid (unsigned int __level, + unsigned int *__eax, unsigned int *__ebx, + unsigned int *__ecx, unsigned int *__edx) +{ + unsigned int __ext = __level & 0x80000000; + + if (__get_cpuid_max (__ext, 0) < __level) + return 0; + + __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx); + return 1; +} -- cgit v1.1