From fd195909ce14c7e852319613e7ec6a9a6e7b99ea Mon Sep 17 00:00:00 2001 From: Przemyslaw Wirkus Date: Wed, 28 Oct 2020 14:01:36 +0000 Subject: aarch64: Add DSB instruction Armv8.7-a variant This patch adds new variant (nXS) of DSB memory barrier instruction available in Armv8.7-a. New nXS variant has different encoding in comparison with pre Armv8.7-a DSB memory barrier variant thus new instruction and new operand was added. DSB memory nXS barrier variant specifies the limitation on the barrier operation. Allowed values are: DSB SYnXS|#28 DSB ISHnXS|#24 DSB NSHnXS|#20 DSB OSHnXS|#16 Please note that till now, for barriers, barrier operation was encoded in 4-bit unsigned immediate CRm field (in the range 0 to 15). For DSB memory nXS barrier variant, barrier operation is a 5-bit unsigned assembly instruction immediate, encoded in instruction in two bits CRm<3:2>: CRm<3:2> #imm 00 16 01 20 10 24 11 28 This patch extends current AArch64 barrier instructions with above mapping. Notable patch changes include: + New DSB memory barrier variant encoding for Armv8.7-a. + New operand BARRIER_DSB_NXS for above instruction in order to distinguish between existing and new DSB instruction flavour. + New set of DSB nXS barrier options. + New instruction inserter and extractor map between instruction immediate 5-bit value and 2-bit CRm field of the instruction itself (see FLD_CRm_dsb_nxs). + Regeneration of aarch64-[asm|dis|opc]-2.c files. + Test cases to cover new instruction assembling and disassembling. For more details regarding DSB memory barrier instruction and its Armv8.7-a flavour please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document pages 132-133 of [0]. [0]: https://developer.arm.com/docs/ddi0596/i gas/ChangeLog: 2020-10-23 Przemyslaw Wirkus * NEWS: Docs update. * config/tc-aarch64.c (parse_operands): Add AARCH64_OPND_BARRIER_DSB_NXS handler. (md_begin): Add content of aarch64_barrier_dsb_nxs_options to aarch64_barrier_opt_hsh hash. * testsuite/gas/aarch64/system-4-invalid.d: New test. * testsuite/gas/aarch64/system-4-invalid.l: New test. * testsuite/gas/aarch64/system-4-invalid.s: New test. * testsuite/gas/aarch64/system-4.d: New test. * testsuite/gas/aarch64/system-4.s: New test. include/ChangeLog: 2020-10-23 Przemyslaw Wirkus * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_BARRIER_DSB_NXS. (aarch64_barrier_dsb_nxs_options): Declare DSB nXS options. opcodes/ChangeLog: 2020-10-23 Przemyslaw Wirkus * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter ins_barrier_dsb_nx. * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor ext_barrier_dsb_nx. * aarch64-opc.c (aarch64_print_operand): New options table aarch64_barrier_dsb_nxs_options. * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs. * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier Armv8.7-a instruction. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. --- gas/NEWS | 2 ++ gas/config/tc-aarch64.c | 47 ++++++++++++++++++++++++++++ gas/testsuite/gas/aarch64/system-4-invalid.d | 3 ++ gas/testsuite/gas/aarch64/system-4-invalid.l | 11 +++++++ gas/testsuite/gas/aarch64/system-4-invalid.s | 16 ++++++++++ gas/testsuite/gas/aarch64/system-4.d | 16 ++++++++++ gas/testsuite/gas/aarch64/system-4.s | 12 +++++++ 7 files changed, 107 insertions(+) create mode 100644 gas/testsuite/gas/aarch64/system-4-invalid.d create mode 100644 gas/testsuite/gas/aarch64/system-4-invalid.l create mode 100644 gas/testsuite/gas/aarch64/system-4-invalid.s create mode 100644 gas/testsuite/gas/aarch64/system-4.d create mode 100644 gas/testsuite/gas/aarch64/system-4.s (limited to 'gas') diff --git a/gas/NEWS b/gas/NEWS index 07fe535..b993464 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -21,6 +21,8 @@ * Add support for Armv8-R and Armv8.7-A AArch64. +* Add support for DSB memory nXS barrier instruction for Armv8.7 AArch64. + * Add support for Intel TDX instructions. * Add support for Intel Key Locker instructions. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index d17d118..2ec1af4 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6686,12 +6686,49 @@ parse_operands (char *str, const aarch64_opcode *opcode) backtrack_pos = 0; goto failure; } + if (val != PARSE_FAIL + && operands[i] == AARCH64_OPND_BARRIER) + { + /* Regular barriers accept options CRm (C0-C15). + DSB nXS barrier variant accepts values > 15. */ + po_imm_or_fail (0, 15); + } /* This is an extension to accept a 0..15 immediate. */ if (val == PARSE_FAIL) po_imm_or_fail (0, 15); info->barrier = aarch64_barrier_options + val; break; + case AARCH64_OPND_BARRIER_DSB_NXS: + val = parse_barrier (&str); + if (val != PARSE_FAIL) + { + /* DSB nXS barrier variant accept only