From c5e7287a1a245a2043352e0db9c731fb7e31a90f Mon Sep 17 00:00:00 2001 From: Ilya Tocar Date: Mon, 17 Nov 2014 14:19:41 +0300 Subject: Add clwb instruction gas/ * config/tc-i386.c (cpu_arch): Add .clwb. * doc/c-i386.texi: Document it. opcodes/ * i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6. (prefix_table): Add clwb. * i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS. (cpu_flags): Add CpuCLWB. * i386-opc.h (enum): Add CpuCLWB. (i386_cpu_flags): Add cpuclwb. * i386-opc.tbl: Add clwb. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. gas/testsuite/ * gas/i386/i386.exp: Run new tests. * gas/i386/clwb-intel.d: New file. * gas/i386/clwb.d: Likewise. * gas/i386/clwb.s: Likewise. * gas/i386/x86-64-clwb-intel.d: Likewise. * gas/i386/x86-64-clwb.d: Likewise. * gas/i386/x86-64-clwb.s: Likewise. --- gas/ChangeLog | 5 +++++ gas/config/tc-i386.c | 2 ++ gas/doc/c-i386.texi | 2 ++ gas/testsuite/ChangeLog | 10 ++++++++++ gas/testsuite/gas/i386/clwb-intel.d | 16 ++++++++++++++++ gas/testsuite/gas/i386/clwb.d | 16 ++++++++++++++++ gas/testsuite/gas/i386/clwb.s | 12 ++++++++++++ gas/testsuite/gas/i386/i386.exp | 4 ++++ gas/testsuite/gas/i386/x86-64-clwb-intel.d | 16 ++++++++++++++++ gas/testsuite/gas/i386/x86-64-clwb.d | 16 ++++++++++++++++ gas/testsuite/gas/i386/x86-64-clwb.s | 12 ++++++++++++ 11 files changed, 111 insertions(+) create mode 100644 gas/testsuite/gas/i386/clwb-intel.d create mode 100644 gas/testsuite/gas/i386/clwb.d create mode 100644 gas/testsuite/gas/i386/clwb.s create mode 100644 gas/testsuite/gas/i386/x86-64-clwb-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-clwb.d create mode 100644 gas/testsuite/gas/i386/x86-64-clwb.s (limited to 'gas') diff --git a/gas/ChangeLog b/gas/ChangeLog index 548fe39..9e85486 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2014-11-17 Ilya Tocar + + * config/tc-i386.c (cpu_arch): Add .clwb. + * doc/c-i386.texi: Document it. + 2014-11-14 H.J. Lu * config/tc-i386.c (cpu_arch): Re-arrange avx512* and xsave* diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 1f9b346..d28230b 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -929,6 +929,8 @@ static const arch_entry cpu_arch[] = CPU_PREFETCHWT1_FLAGS, 0, 0 }, { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, CPU_SE1_FLAGS, 0, 0 }, + { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, + CPU_CLWB_FLAGS, 0, 0 }, }; #ifdef I386COFF diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 440f375..f3a1eec 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -154,6 +154,7 @@ accept various extension mnemonics. For example, @code{prefetchwt1}, @code{clflushopt}, @code{se1}, +@code{clwb}, @code{avx512f}, @code{avx512cd}, @code{avx512er}, @@ -1103,6 +1104,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1} @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf} @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} +@item @samp{.clwb} @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm} @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 7908363..6fa1604 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,13 @@ +2014-11-17 Ilya Tocar + + * gas/i386/i386.exp: Run new tests. + * gas/i386/clwb-intel.d: New file. + * gas/i386/clwb.d: Likewise. + * gas/i386/clwb.s: Likewise. + * gas/i386/x86-64-clwb-intel.d: Likewise. + * gas/i386/x86-64-clwb.d: Likewise. + * gas/i386/x86-64-clwb.s: Likewise. + 2014-11-13 H.J. Lu PR gas/17598 diff --git a/gas/testsuite/gas/i386/clwb-intel.d b/gas/testsuite/gas/i386/clwb-intel.d new file mode 100644 index 0000000..395f4c4 --- /dev/null +++ b/gas/testsuite/gas/i386/clwb-intel.d @@ -0,0 +1,16 @@ +#as: +#objdump: -dw -Mintel +#name: i386 CLWB insns (Intel disassembly) +#source: clwb.s + +.*: +file format .* + + +Disassembly of section \.text: + +00000000 <_start>: +[ ]*[a-f0-9]+:[ ]*66 0f ae 31[ ]*clwb BYTE PTR \[ecx\] +[ ]*[a-f0-9]+:[ ]*66 0f ae b4 f4 c0 1d fe ff[ ]*clwb BYTE PTR \[esp\+esi\*8-0x1e240\] +[ ]*[a-f0-9]+:[ ]*66 0f ae 31[ ]*clwb BYTE PTR \[ecx\] +[ ]*[a-f0-9]+:[ ]*66 0f ae b4 f4 c0 1d fe ff[ ]*clwb BYTE PTR \[esp\+esi\*8-0x1e240\] +#pass diff --git a/gas/testsuite/gas/i386/clwb.d b/gas/testsuite/gas/i386/clwb.d new file mode 100644 index 0000000..aa2a2be --- /dev/null +++ b/gas/testsuite/gas/i386/clwb.d @@ -0,0 +1,16 @@ +#as: +#objdump: -dw +#name: i386 CLWB insns +#source: clwb.s + +.*: +file format .* + + +Disassembly of section \.text: + +00000000 <_start>: +[ ]*[a-f0-9]+:[ ]*66 0f ae 31[ ]*clwb \(%ecx\) +[ ]*[a-f0-9]+:[ ]*66 0f ae b4 f4 c0 1d fe ff[ ]*clwb -0x1e240\(%esp,%esi,8\) +[ ]*[a-f0-9]+:[ ]*66 0f ae 31[ ]*clwb \(%ecx\) +[ ]*[a-f0-9]+:[ ]*66 0f ae b4 f4 c0 1d fe ff[ ]*clwb -0x1e240\(%esp,%esi,8\) +#pass diff --git a/gas/testsuite/gas/i386/clwb.s b/gas/testsuite/gas/i386/clwb.s new file mode 100644 index 0000000..8132218 --- /dev/null +++ b/gas/testsuite/gas/i386/clwb.s @@ -0,0 +1,12 @@ +# Check 32bit CLWB instructions + + .allow_index_reg + .text +_start: + + clwb (%ecx) # CLWB + clwb -123456(%esp,%esi,8) # CLWB + + .intel_syntax noprefix + clwb BYTE PTR [ecx] # CLWB + clwb BYTE PTR [esp+esi*8-123456] # CLWB diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index c55f3bf..4d85105 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -330,6 +330,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_dump_test "avx512f-rcigru" run_dump_test "avx512f-rcigrz-intel" run_dump_test "avx512f-rcigrz" + run_dump_test "clwb" + run_dump_test "clwb-intel" run_dump_test "disassem" # These tests require support for 8 and 16 bit relocs, @@ -681,6 +683,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-avx512f-rcigru" run_dump_test "x86-64-avx512f-rcigrz-intel" run_dump_test "x86-64-avx512f-rcigrz" + run_dump_test "x86-64-clwb" + run_dump_test "x86-64-clwb-intel" if { ![istarget "*-*-aix*"] && ![istarget "*-*-beos*"] diff --git a/gas/testsuite/gas/i386/x86-64-clwb-intel.d b/gas/testsuite/gas/i386/x86-64-clwb-intel.d new file mode 100644 index 0000000..5995c78 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-clwb-intel.d @@ -0,0 +1,16 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 CLWB insns (Intel disassembly) +#source: x86-64-clwb.s + +.*: +file format .* + + +Disassembly of section \.text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*66 0f ae 31[ ]*clwb BYTE PTR \[rcx\] +[ ]*[a-f0-9]+:[ ]*66 42 0f ae b4 f0 23 01 00 00[ ]*clwb BYTE PTR \[rax\+r14\*8\+0x123\] +[ ]*[a-f0-9]+:[ ]*66 0f ae 31[ ]*clwb BYTE PTR \[rcx\] +[ ]*[a-f0-9]+:[ ]*66 42 0f ae b4 f0 34 12 00 00[ ]*clwb BYTE PTR \[rax\+r14\*8\+0x1234\] +#pass diff --git a/gas/testsuite/gas/i386/x86-64-clwb.d b/gas/testsuite/gas/i386/x86-64-clwb.d new file mode 100644 index 0000000..eee47dd --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-clwb.d @@ -0,0 +1,16 @@ +#as: +#objdump: -dw +#name: x86_64 CLWB insns +#source: x86-64-clwb.s + +.*: +file format .* + + +Disassembly of section \.text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*66 0f ae 31[ ]*clwb \(%rcx\) +[ ]*[a-f0-9]+:[ ]*66 42 0f ae b4 f0 23 01 00 00[ ]*clwb 0x123\(%rax,%r14,8\) +[ ]*[a-f0-9]+:[ ]*66 0f ae 31[ ]*clwb \(%rcx\) +[ ]*[a-f0-9]+:[ ]*66 42 0f ae b4 f0 34 12 00 00[ ]*clwb 0x1234\(%rax,%r14,8\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-clwb.s b/gas/testsuite/gas/i386/x86-64-clwb.s new file mode 100644 index 0000000..817fe9e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-clwb.s @@ -0,0 +1,12 @@ +# Check 64bit CLWB instructions + + .allow_index_reg + .text +_start: + + clwb (%rcx) # CLWB + clwb 0x123(%rax,%r14,8) # CLWB + + .intel_syntax noprefix + clwb BYTE PTR [rcx] # CLWB + clwb BYTE PTR [rax+r14*8+0x1234] # CLWB -- cgit v1.1