From b416fe873ef44b2a613c9266c6462a481926d986 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Tue, 7 Mar 2017 18:15:02 +0800 Subject: RISC-V: Fix assembler for c.li, c.andi and c.addiw - They can accept 0 in imm field 2017-03-14 Kito Cheng * riscv-opc.c (riscv_opcodes> : Use the 'o' immediate encoding. : Likewise. Likewise. --- gas/ChangeLog | 6 ++++++ gas/config/tc-riscv.c | 8 ++++++++ 2 files changed, 14 insertions(+) (limited to 'gas') diff --git a/gas/ChangeLog b/gas/ChangeLog index e376e30..58a7327 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2017-03-14 Kito Cheng + + * config/tc-riscv.c (validate_riscv_insn): Add 'o' RVC immediate + encoding format, which can accept 0-valued immediates. + (riscv_ip): Likewise. + 2017-03-15 Nick Clifton * config/tc-riscv.c (riscv_pre_output_hook): Fix compile time diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 79211f3..ff6d737 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -506,6 +506,7 @@ validate_riscv_insn (const struct riscv_opcode *opc) case 'c': break; /* RS1, constrained to equal sp */ case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break; case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break; + case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break; case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break; case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break; case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break; @@ -1327,6 +1328,13 @@ rvc_imm_done: ip->insn_opcode |= ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number); goto rvc_imm_done; + case 'o': + if (my_getSmallExpression (imm_expr, imm_reloc, s, p) + || imm_expr->X_op != O_constant + || !VALID_RVC_IMM (imm_expr->X_add_number)) + break; + ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); + goto rvc_imm_done; case 'K': if (my_getSmallExpression (imm_expr, imm_reloc, s, p) || imm_expr->X_op != O_constant -- cgit v1.1