From 6f1c2142595b1ec203a7da998b2155403a433e89 Mon Sep 17 00:00:00 2001 From: Alessandro Marzocchi Date: Thu, 16 Jul 2015 16:38:48 +0100 Subject: Updates the ARM disassembler's output of floating point constants to include the actual floating point value. opcodes * arm-dis.c (print_insn_coprocessor): Added support for quarter float bitfield format. (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new quarter float bitfield format. tests * gas/arm/vfpv3-const-conv.d: Update expected result due to change of comment for vmov reg,immediate with VFP coprocessor. --- gas/testsuite/gas/arm/vfpv3-const-conv.d | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'gas') diff --git a/gas/testsuite/gas/arm/vfpv3-const-conv.d b/gas/testsuite/gas/arm/vfpv3-const-conv.d index d8d244d..f9cb513 100644 --- a/gas/testsuite/gas/arm/vfpv3-const-conv.d +++ b/gas/testsuite/gas/arm/vfpv3-const-conv.d @@ -5,10 +5,10 @@ .*: +file format .*arm.* Disassembly of section \.text: -0[0-9a-f]+ <[^>]+> eef08a04 (vmov\.f32|fconsts) s17, #4 +0[0-9a-f]+ <[^>]+> eef08a04 (vmov\.f32|fconsts) s17, #4.* 0[0-9a-f]+ <[^>]+> eeba9a05 (vmov\.f32|fconsts) s18, #165.* 0[0-9a-f]+ <[^>]+> eef49a00 (vmov\.f32|fconsts) s19, #64.* -0[0-9a-f]+ <[^>]+> eef01b04 (vmov\.f64|fconstd) d17, #4 +0[0-9a-f]+ <[^>]+> eef01b04 (vmov\.f64|fconstd) d17, #4.* 0[0-9a-f]+ <[^>]+> eefa2b05 (vmov\.f64|fconstd) d18, #165.* 0[0-9a-f]+ <[^>]+> eef43b00 (vmov\.f64|fconstd) d19, #64.* 0[0-9a-f]+ <[^>]+> eefa8a63 (vcvt\.f32\.s16 s17, s17, #9|fshtos s17, #9) -- cgit v1.1