From 550fd7bf6858cd708c54ec90412ffb653a932c3d Mon Sep 17 00:00:00 2001 From: Sudi Das Date: Fri, 25 Jan 2019 13:57:14 +0000 Subject: AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Extension. This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV instructions. These instructions needed special infrastructure to support [base]! style for addressing mode. That is also removed now. Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * config/tc-aarch64.c (parse_address_main): Remove support for [base]! address expression. (parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2. (warn_unpredictable_ldst): Remove support for ldstgv_indexed. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv and stgv. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** include/ChangeLog *** * opcode/aarch64.h (enum aarch64_opnd): Remove AARCH64_OPND_ADDR_SIMPLE_2. (enum aarch64_insn_class): Remove ldstgv_indexed. *** opcodes/ChangeLog *** * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. * aarch64-asm.h (ins_addr_simple_2): Likeiwse. * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. * aarch64-dis.h (ext_addr_simple_2): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Remove case for ldstgv_indexed. (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. --- gas/ChangeLog | 13 +++++++++++++ gas/config/tc-aarch64.c | 19 +++---------------- gas/testsuite/gas/aarch64/armv8_5-a-memtag.d | 11 ----------- gas/testsuite/gas/aarch64/armv8_5-a-memtag.s | 13 ------------- gas/testsuite/gas/aarch64/illegal-memtag.l | 7 ------- gas/testsuite/gas/aarch64/illegal-memtag.s | 12 ------------ 6 files changed, 16 insertions(+), 59 deletions(-) (limited to 'gas') diff --git a/gas/ChangeLog b/gas/ChangeLog index 50eea84..bd62c75 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,16 @@ +2019-01-25 Sudakshina Das + Ramana Radhakrishnan + + * config/tc-aarch64.c (parse_address_main): Remove support for + [base]! address expression. + (parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2. + (warn_unpredictable_ldst): Remove support for ldstgv_indexed. + * testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv + and stgv. + * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. + * testsuite/gas/aarch64/illegal-memtag.l: Likewise. + * testsuite/gas/aarch64/illegal-memtag.s: Likewise. + 2019-01-25 Wu Heng PR gas/23940 diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 461c39b..537f00c 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -3381,7 +3381,6 @@ parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand, [base,Wm,(S|U)XTW {#imm}] Pre-indexed [base,#imm]! - [base]! // in ld/stgv Post-indexed [base],#imm [base],Xm // in SIMD ld/st structure @@ -3690,11 +3689,10 @@ parse_address_main (char **str, aarch64_opnd_info *operand, } /* If at this point neither .preind nor .postind is set, we have a - bare [Rn]{!}; reject [Rn]! except for ld/stgv but accept [Rn] - as a shorthand for [Rn,#0]. */ + bare [Rn]{!}; reject [Rn]! accept [Rn] as a shorthand for [Rn,#0]. */ if (operand->addr.preind == 0 && operand->addr.postind == 0) { - if (operand->type != AARCH64_OPND_ADDR_SIMPLE_2 && operand->addr.writeback) + if (operand->addr.writeback) { /* Reject [Rn]! */ set_syntax_error (_("missing offset in the pre-indexed address")); @@ -6148,7 +6146,6 @@ parse_operands (char *str, const aarch64_opcode *opcode) break; case AARCH64_OPND_ADDR_SIMPLE: - case AARCH64_OPND_ADDR_SIMPLE_2: case AARCH64_OPND_SIMD_ADDR_SIMPLE: { /* [{, #}] */ @@ -6158,8 +6155,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) po_misc_or_fail (parse_address (&str, info)); if (info->addr.pcrel || info->addr.offset.is_reg || !info->addr.preind || info->addr.postind - || (info->addr.writeback - && operands[i] != AARCH64_OPND_ADDR_SIMPLE_2)) + || info->addr.writeback) { set_syntax_error (_("invalid addressing mode")); goto failure; @@ -6182,8 +6178,6 @@ parse_operands (char *str, const aarch64_opcode *opcode) } } po_char_or_fail (']'); - if (operands[i] == AARCH64_OPND_ADDR_SIMPLE_2) - po_char_or_fail ('!'); break; } @@ -6782,13 +6776,6 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str) as_warn (_("unpredictable transfer with writeback -- `%s'"), str); break; - case ldstgv_indexed: - /* Load operations must load different registers. */ - if ((opcode->opcode & (1 << 22)) - && opnds[0].reg.regno == opnds[1].addr.base_regno) - as_warn (_("unpredictable load of register -- `%s'"), str); - break; - case ldstpair_off: case ldstnapair_offs: case ldstpair_indexed: diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d index fa56bfa..363bbe2 100644 --- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d +++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d @@ -121,14 +121,3 @@ Disassembly of section \.text: .*: d960001f ldg xzr, \[x0\] .*: d96ff000 ldg x0, \[x0, #4080\] .*: d9700000 ldg x0, \[x0, #-4096\] -.*: d9e0001b ldgv x27, \[x0\]! -.*: d9e00360 ldgv x0, \[x27\]! -.*: d9e00379 ldgv x25, \[x27\]! -.*: d9e003e0 ldgv x0, \[sp\]! -.*: d9e0001f ldgv xzr, \[x0\]! -.*: d9a00000 stgv x0, \[x0\]! -.*: d9a0001b stgv x27, \[x0\]! -.*: d9a00360 stgv x0, \[x27\]! -.*: d9a00379 stgv x25, \[x27\]! -.*: d9a003e0 stgv x0, \[sp\]! -.*: d9a0001f stgv xzr, \[x0\]! diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s index 2c2ff8f..62c9436 100644 --- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s +++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s @@ -30,14 +30,6 @@ func: \op [sp], #-4096 .endm - .macro expand_ldg_bulk op - \op x27, [x0]! - \op x0, [x27]! - \op x25, [x27]! - \op x0, [sp]! - \op xzr, [x0]! - .endm - # IRG expand_3_reg irg irg sp, x0 @@ -106,8 +98,3 @@ func: ldg xzr, [x0, #0] ldg x0, [x0, #4080] ldg x0, [x0, #-4096] - - expand_ldg_bulk ldgv - - stgv x0, [x0]! - expand_ldg_bulk stgv diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l index 0d499d9..dfdf00a 100644 --- a/gas/testsuite/gas/aarch64/illegal-memtag.l +++ b/gas/testsuite/gas/aarch64/illegal-memtag.l @@ -12,9 +12,6 @@ [^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#1009\]' [^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 3 -- `stgp x1,x2,\[x3,#33\]' [^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#-1025\]' -[^:]*:[0-9]+: Warning: unpredictable load of register -- `ldgv x1,\[x1\]!' -[^:]*:[0-9]+: Error: operand 2 must be a writeback address with base register \(no offset\) -- `ldgv x1,\[x2\]' -[^:]*:[0-9]+: Error: operand 2 must be a writeback address with base register \(no offset\) -- `stgv x1,\[x2\]' [^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3' [^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3' [^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp' @@ -40,7 +37,3 @@ [^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]' [^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldg sp,\[x0,#16\]' [^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldg x0,\[xzr,#16\]' -[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldgv sp,\[x1\]!' -[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldgv x0,\[xzr\]!' -[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgv sp,\[x1\]!' -[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stgv x0,\[xzr\]!' diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.s b/gas/testsuite/gas/aarch64/illegal-memtag.s index 7b7dcd9..35d1b12 100644 --- a/gas/testsuite/gas/aarch64/illegal-memtag.s +++ b/gas/testsuite/gas/aarch64/illegal-memtag.s @@ -20,14 +20,6 @@ func: stgp x1, x2, [x3, #33] stgp x1, x2, [x3, #-1025] - # LDGV : Warn for Xt == Xn - # STGV : Sould not warn for above - ldgv x1, [x1]! - stgv x1, [x1]! - # Error for no writeback - ldgv x1, [x2] - stgv x1, [x2] - # Illegal SP/XZR registers irg xzr, x2, x3 irg x1, xzr, x3 @@ -54,7 +46,3 @@ func: stgp x0, x0, [xzr] ldg sp, [x0, #16] ldg x0, [xzr, #16] - ldgv sp, [x1]! - ldgv x0, [xzr]! - stgv sp, [x1]! - stgv x0, [xzr]! -- cgit v1.1