From 100b4f2e9f65565e3e3e484162c4474effc54be8 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Mon, 18 Jan 2016 21:29:37 +0000 Subject: MIPS: Remove remnants of 48-bit microMIPS instruction support The POOL48A major opcode was defined in early revisions of the 64-bit microMIPS ISA, has never been implemented, and was removed before the 64-bit microMIPS ISA specification[1] has been finalized. This complements commit a6c7053929dd ("MIPS/opcodes: Remove microMIPS 48-bit LI instruction"). References: [1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64 Instruction Set", MIPS Technologies, Inc., Document Number: MD00594, Revision 3.06, October 17, 2012, Table 6.2 "microMIPS64 Encoding of Major Opcode Field", p. 578 gas/ * config/tc-mips.c (micromips_insn_length): Remove the mention of 48-bit microMIPS instructions. gdb/ * mips-tdep.c (mips_insn_size): Remove 48-bit microMIPS instruction support. (micromips_next_pc): Likewise. (micromips_scan_prologue): Likewise. (micromips_deal_with_atomic_sequence): Likewise. (micromips_stack_frame_destroyed_p): Likewise. (mips_breakpoint_from_pc): Likewise. opcodes/ * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS instruction support. --- gas/ChangeLog | 5 +++++ gas/config/tc-mips.c | 6 ++---- 2 files changed, 7 insertions(+), 4 deletions(-) (limited to 'gas') diff --git a/gas/ChangeLog b/gas/ChangeLog index 1c0e224..a905d6f 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2016-01-18 Maciej W. Rozycki + + * config/tc-mips.c (micromips_insn_length): Remove the mention + of 48-bit microMIPS instructions. + 2016-01-18 Alan Modra * configure: Regenerate. diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 859ddc6..d577774 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -2089,10 +2089,8 @@ mips_lookup_ase (const char *name) } /* Return the length of a microMIPS instruction in bytes. If bits of - the mask beyond the low 16 are 0, then it is a 16-bit instruction. - Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f - major opcode) will require further modifications to the opcode - table. */ + the mask beyond the low 16 are 0, then it is a 16-bit instruction, + otherwise it is a 32-bit instruction. */ static inline unsigned int micromips_insn_length (const struct mips_opcode *mo) -- cgit v1.1