From 643afb90da9066e9d3c6dc721920b14ed343bec9 Mon Sep 17 00:00:00 2001 From: Matthew Wahab Date: Fri, 4 Mar 2016 11:28:28 +0000 Subject: [ARM] Add feature check for ARMv8.1 AdvSIMD instructions. gas/ 2016-03-04 Matthew Wahab * config/gas/tc-arm.c (fpu_neon_ext_v8_1): Restrict to the ARMv8.1 RDMA feature. (record_feature_use): New. (mark_feature_used): Use record_feature_use. (do_neon_qrdmlah): New. (insns): Use do_neon_qrdmlah for vqrdmlah and vqrdmlsh and variants. (arm_extensions): Put into alphabetical order. Re-indent "simd" and "rdma" entries. Fix the incorrect merge value for "+rdma". * testsuite/gas/arm/armv8-a+rdma-warning.d: New. * testsuite/gas/arm/armv8-a+rdma.d: Add assembler command line options. Make source file explicit. * testsuite/gas/arm/armv8-a+rdma.l: New. * testsuite/gas/arm/armv8-a+rdma.s: Remove .arch and .arch_extension directives. Fix white-space. * testsuite/gas/arm/armv8_1-a+simd.d: New. include/opcode 2016-03-04 Matthew Wahab * arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA. (ARM_CPU_HAS_FEATURE): Add comment. Change-Id: Ie19250e8fa50aed44e44ab40ff30b04b38bc1a3d --- gas/testsuite/gas/arm/armv8-a+rdma-warning.d | 6 +++ gas/testsuite/gas/arm/armv8-a+rdma.d | 2 + gas/testsuite/gas/arm/armv8-a+rdma.l | 65 +++++++++++++++++++++++ gas/testsuite/gas/arm/armv8-a+rdma.s | 64 +++++++++++------------ gas/testsuite/gas/arm/armv8_1-a+simd.d | 78 ++++++++++++++++++++++++++++ 5 files changed, 182 insertions(+), 33 deletions(-) create mode 100644 gas/testsuite/gas/arm/armv8-a+rdma-warning.d create mode 100644 gas/testsuite/gas/arm/armv8-a+rdma.l create mode 100644 gas/testsuite/gas/arm/armv8_1-a+simd.d (limited to 'gas/testsuite') diff --git a/gas/testsuite/gas/arm/armv8-a+rdma-warning.d b/gas/testsuite/gas/arm/armv8-a+rdma-warning.d new file mode 100644 index 0000000..da54c4d --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a+rdma-warning.d @@ -0,0 +1,6 @@ +#name: Accepted v8-a with ARMv8.1 AdvSIMD. +#as: -march=armv8-a+simd +#objdump: -dr +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd +#source: armv8-a+rdma.s +#error-output: armv8-a+rdma.l \ No newline at end of file diff --git a/gas/testsuite/gas/arm/armv8-a+rdma.d b/gas/testsuite/gas/arm/armv8-a+rdma.d index 3242b53..d30aab7 100644 --- a/gas/testsuite/gas/arm/armv8-a+rdma.d +++ b/gas/testsuite/gas/arm/armv8-a+rdma.d @@ -1,6 +1,8 @@ #name: Valid v8-a+rdma +#as: -march=armv8-a+rdma #objdump: -dr #skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd +#source: armv8-a+rdma.s .*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/armv8-a+rdma.l b/gas/testsuite/gas/arm/armv8-a+rdma.l new file mode 100644 index 0000000..540e392 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8-a+rdma.l @@ -0,0 +1,65 @@ +[^:]+: Assembler messages: +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. +[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD. diff --git a/gas/testsuite/gas/arm/armv8-a+rdma.s b/gas/testsuite/gas/arm/armv8-a+rdma.s index 60632f5..f89786f 100644 --- a/gas/testsuite/gas/arm/armv8-a+rdma.s +++ b/gas/testsuite/gas/arm/armv8-a+rdma.s @@ -1,60 +1,58 @@ .syntax unified .text - .arch armv8-a - .arch_extension rdma - .macro vect_inst I T R - \I\().\T \R\()0, \R\()1, \R\()2 - .endm + .macro vect_inst I T R + \I\().\T \R\()0, \R\()1, \R\()2 + .endm .macro scalar_inst I T R N - \I\().\T \R\()0, \R\()1, d\()2[\N\()] - .endm + \I\().\T \R\()0, \R\()1, d\()2[\N\()] + .endm .text - .arm + .arm A1: - .irp inst, vqrdmlah, vqrdmlsh - .irp type, s16, s32 + .irp inst, vqrdmlah, vqrdmlsh + .irp type, s16, s32 .irp reg, d, q - vect_inst \inst \type \reg - .endr - .endr + vect_inst \inst \type \reg + .endr + .endr .endr - .irp inst, vqrdmlah, vqrdmlsh + .irp inst, vqrdmlah, vqrdmlsh .irp reg, d, q - .irp idx, 0, 1, 2, 3 - scalar_inst \inst s16 \reg \idx - .endr + .irp idx, 0, 1, 2, 3 + scalar_inst \inst s16 \reg \idx + .endr .endr .irp reg, d, q - .irp idx, 0, 1 - scalar_inst \inst s32 \reg \idx - .endr + .irp idx, 0, 1 + scalar_inst \inst s32 \reg \idx + .endr .endr .endr .text - .thumb + .thumb T1: - .irp inst, vqrdmlah, vqrdmlsh - .irp type, s16, s32 + .irp inst, vqrdmlah, vqrdmlsh + .irp type, s16, s32 .irp reg, d, q - vect_inst \inst \type \reg - .endr - .endr + vect_inst \inst \type \reg + .endr + .endr .endr - .irp inst, vqrdmlah, vqrdmlsh + .irp inst, vqrdmlah, vqrdmlsh .irp reg, d, q - .irp idx, 0, 1, 2, 3 - scalar_inst \inst s16 \reg \idx - .endr + .irp idx, 0, 1, 2, 3 + scalar_inst \inst s16 \reg \idx + .endr .endr .irp reg, d, q - .irp idx, 0, 1 - scalar_inst \inst s32 \reg \idx - .endr + .irp idx, 0, 1 + scalar_inst \inst s32 \reg \idx + .endr .endr .endr diff --git a/gas/testsuite/gas/arm/armv8_1-a+simd.d b/gas/testsuite/gas/arm/armv8_1-a+simd.d new file mode 100644 index 0000000..2bb2713 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_1-a+simd.d @@ -0,0 +1,78 @@ +#name: Valid ARMv8.1-A with +simd +#as: -march=armv8.1-a+simd +#objdump: -dr +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd +#source: armv8-a+rdma.s + +.*: +file format .*arm.* + + +Disassembly of section .text: + +00000000 <.*>: + 0: f3110b12 vqrdmlah.s16 d0, d1, d2 + 4: f3120b54 vqrdmlah.s16 q0, q1, q2 + 8: f3210b12 vqrdmlah.s32 d0, d1, d2 + c: f3220b54 vqrdmlah.s32 q0, q1, q2 + 10: f3110c12 vqrdmlsh.s16 d0, d1, d2 + 14: f3120c54 vqrdmlsh.s16 q0, q1, q2 + 18: f3210c12 vqrdmlsh.s32 d0, d1, d2 + 1c: f3220c54 vqrdmlsh.s32 q0, q1, q2 + 20: f2910e42 vqrdmlah.s16 d0, d1, d2\[0\] + 24: f2910e4a vqrdmlah.s16 d0, d1, d2\[1\] + 28: f2910e62 vqrdmlah.s16 d0, d1, d2\[2\] + 2c: f2910e6a vqrdmlah.s16 d0, d1, d2\[3\] + 30: f3920e42 vqrdmlah.s16 q0, q1, d2\[0\] + 34: f3920e4a vqrdmlah.s16 q0, q1, d2\[1\] + 38: f3920e62 vqrdmlah.s16 q0, q1, d2\[2\] + 3c: f3920e6a vqrdmlah.s16 q0, q1, d2\[3\] + 40: f2a10e42 vqrdmlah.s32 d0, d1, d2\[0\] + 44: f2a10e62 vqrdmlah.s32 d0, d1, d2\[1\] + 48: f3a20e42 vqrdmlah.s32 q0, q1, d2\[0\] + 4c: f3a20e62 vqrdmlah.s32 q0, q1, d2\[1\] + 50: f2910f42 vqrdmlsh.s16 d0, d1, d2\[0\] + 54: f2910f4a vqrdmlsh.s16 d0, d1, d2\[1\] + 58: f2910f62 vqrdmlsh.s16 d0, d1, d2\[2\] + 5c: f2910f6a vqrdmlsh.s16 d0, d1, d2\[3\] + 60: f3920f42 vqrdmlsh.s16 q0, q1, d2\[0\] + 64: f3920f4a vqrdmlsh.s16 q0, q1, d2\[1\] + 68: f3920f62 vqrdmlsh.s16 q0, q1, d2\[2\] + 6c: f3920f6a vqrdmlsh.s16 q0, q1, d2\[3\] + 70: f2a10f42 vqrdmlsh.s32 d0, d1, d2\[0\] + 74: f2a10f62 vqrdmlsh.s32 d0, d1, d2\[1\] + 78: f3a20f42 vqrdmlsh.s32 q0, q1, d2\[0\] + 7c: f3a20f62 vqrdmlsh.s32 q0, q1, d2\[1\] + +00000080 <.*>: + 80: ff11 0b12 vqrdmlah.s16 d0, d1, d2 + 84: ff12 0b54 vqrdmlah.s16 q0, q1, q2 + 88: ff21 0b12 vqrdmlah.s32 d0, d1, d2 + 8c: ff22 0b54 vqrdmlah.s32 q0, q1, q2 + 90: ff11 0c12 vqrdmlsh.s16 d0, d1, d2 + 94: ff12 0c54 vqrdmlsh.s16 q0, q1, q2 + 98: ff21 0c12 vqrdmlsh.s32 d0, d1, d2 + 9c: ff22 0c54 vqrdmlsh.s32 q0, q1, q2 + a0: ef91 0e42 vqrdmlah.s16 d0, d1, d2\[0\] + a4: ef91 0e4a vqrdmlah.s16 d0, d1, d2\[1\] + a8: ef91 0e62 vqrdmlah.s16 d0, d1, d2\[2\] + ac: ef91 0e6a vqrdmlah.s16 d0, d1, d2\[3\] + b0: ff92 0e42 vqrdmlah.s16 q0, q1, d2\[0\] + b4: ff92 0e4a vqrdmlah.s16 q0, q1, d2\[1\] + b8: ff92 0e62 vqrdmlah.s16 q0, q1, d2\[2\] + bc: ff92 0e6a vqrdmlah.s16 q0, q1, d2\[3\] + c0: efa1 0e42 vqrdmlah.s32 d0, d1, d2\[0\] + c4: efa1 0e62 vqrdmlah.s32 d0, d1, d2\[1\] + c8: ffa2 0e42 vqrdmlah.s32 q0, q1, d2\[0\] + cc: ffa2 0e62 vqrdmlah.s32 q0, q1, d2\[1\] + d0: ef91 0f42 vqrdmlsh.s16 d0, d1, d2\[0\] + d4: ef91 0f4a vqrdmlsh.s16 d0, d1, d2\[1\] + d8: ef91 0f62 vqrdmlsh.s16 d0, d1, d2\[2\] + dc: ef91 0f6a vqrdmlsh.s16 d0, d1, d2\[3\] + e0: ff92 0f42 vqrdmlsh.s16 q0, q1, d2\[0\] + e4: ff92 0f4a vqrdmlsh.s16 q0, q1, d2\[1\] + e8: ff92 0f62 vqrdmlsh.s16 q0, q1, d2\[2\] + ec: ff92 0f6a vqrdmlsh.s16 q0, q1, d2\[3\] + f0: efa1 0f42 vqrdmlsh.s32 d0, d1, d2\[0\] + f4: efa1 0f62 vqrdmlsh.s32 d0, d1, d2\[1\] + f8: ffa2 0f42 vqrdmlsh.s32 q0, q1, d2\[0\] + fc: ffa2 0f62 vqrdmlsh.s32 q0, q1, d2\[1\] -- cgit v1.1