From 18a8a00ebe3159b65798c6132cb5f93ff4ef6c17 Mon Sep 17 00:00:00 2001 From: Alan Modra Date: Wed, 19 Aug 2020 08:47:35 +0930 Subject: Correct vcmpsq, vcmpuq and xvtlsbb BF field These shouldn't be optional. The record form of vector instructions set CR6, giving an expectation that omitting BF should be the same as specifying CR6. opcodes/ * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq, vcmpuq and xvtlsbb. gas/ * testsuite/gas/ppc/int128.s: Correct vcmpuq. * testsuite/gas/ppc/int128.d: Update. * testsuite/gas/ppc/xvtlsbb.d: Update. --- gas/testsuite/gas/ppc/int128.d | 2 +- gas/testsuite/gas/ppc/int128.s | 2 +- gas/testsuite/gas/ppc/xvtlsbb.d | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'gas/testsuite') diff --git a/gas/testsuite/gas/ppc/int128.d b/gas/testsuite/gas/ppc/int128.d index c9f14d3..d741034 100644 --- a/gas/testsuite/gas/ppc/int128.d +++ b/gas/testsuite/gas/ppc/int128.d @@ -20,7 +20,7 @@ Disassembly of section \.text: .*: (13 9d f7 0b|0b f7 9d 13) vmodsq v28,v29,v30 .*: (13 e0 0e 0b|0b 0e e0 13) vmoduq v31,v0,v1 .*: (10 5b 1e 02|02 1e 5b 10) vextsd2q v2,v3 -.*: (10 04 29 01|01 29 04 10) vcmpuq v4,v5 +.*: (10 04 29 01|01 29 04 10) vcmpuq cr0,v4,v5 .*: (10 86 39 41|41 39 86 10) vcmpsq cr1,v6,v7 .*: (11 09 51 c7|c7 51 09 11) vcmpequq v8,v9,v10 .*: (11 6c 6d c7|c7 6d 6c 11) vcmpequq. v11,v12,v13 diff --git a/gas/testsuite/gas/ppc/int128.s b/gas/testsuite/gas/ppc/int128.s index 4dce648..4561cfe 100644 --- a/gas/testsuite/gas/ppc/int128.s +++ b/gas/testsuite/gas/ppc/int128.s @@ -12,7 +12,7 @@ _start: vmodsq 28,29,30 vmoduq 31,0,1 vextsd2q 2,3 - vcmpuq 4,5 + vcmpuq 0,4,5 vcmpsq 1,6,7 vcmpequq 8,9,10 vcmpequq. 11,12,13 diff --git a/gas/testsuite/gas/ppc/xvtlsbb.d b/gas/testsuite/gas/ppc/xvtlsbb.d index 1627d7a..8aa83dd 100644 --- a/gas/testsuite/gas/ppc/xvtlsbb.d +++ b/gas/testsuite/gas/ppc/xvtlsbb.d @@ -7,7 +7,7 @@ Disassembly of section \.text: 0+0 <_start>: -.*: (f0 02 ff 6e|6e ff 02 f0) xvtlsbb vs63 +.*: (f0 02 ff 6e|6e ff 02 f0) xvtlsbb cr0,vs63 .*: (f0 82 07 6c|6c 07 82 f0) xvtlsbb cr1,vs0 .*: (f1 02 f7 6e|6e f7 02 f1) xvtlsbb cr2,vs62 .*: (f1 82 0f 6c|6c 0f 82 f1) xvtlsbb cr3,vs1 -- cgit v1.1