From fb3265b371a141c4ffc97dcf8cc66e090c516dc8 Mon Sep 17 00:00:00 2001 From: Sudakshina Das Date: Mon, 12 Nov 2018 13:09:55 +0000 Subject: [BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Extension This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Tag setting instructions from MTE which consists of the following instructions: - STG [, #] - STG [, #]! - STG [], # - STZG [, #] - STZG [, #]! - STZG [], # - ST2G [, #] - ST2G [, #]! - ST2G [], # - STZ2G [, #] - STZ2G [, #]! - STZ2G [], # - STGP , , [, #] - STGP , , [, #]! - STGP , , [], # where : Is the 64-bit GPR or Stack pointer. : Is the optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0. *** include/ChangeLog *** 2018-11-12 Sudakshina Das * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data for AARCH64_OPND_QLF_imm_tag. (operand_general_constraint_met_p): Add case for AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New. (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp for both offset and pre/post indexed versions. (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (fix_insn): Likewise. (warn_unpredictable_ldst): Exempt STGP. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g, stzg, stz2g and stgp. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. --- gas/config/tc-aarch64.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'gas/config') diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 5f79e92..a5eee96 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6214,6 +6214,8 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_ADDR_SIMM9: case AARCH64_OPND_ADDR_SIMM9_2: + case AARCH64_OPND_ADDR_SIMM11: + case AARCH64_OPND_ADDR_SIMM13: po_misc_or_fail (parse_address (&str, info)); if (info->addr.pcrel || info->addr.offset.is_reg || (!info->addr.preind && !info->addr.postind) @@ -6773,6 +6775,8 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str) && (opnds[0].reg.regno == opnds[2].addr.base_regno || opnds[1].reg.regno == opnds[2].addr.base_regno) && opnds[2].addr.base_regno != REG_SP + /* Exempt STGP. */ + && !(opnds[2].type == AARCH64_OPND_ADDR_SIMM11) && opnds[2].addr.writeback) as_warn (_("unpredictable transfer with writeback -- `%s'"), str); /* Load operations must load different registers. */ @@ -7674,6 +7678,8 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value) case AARCH64_OPND_ADDR_SIMM9_2: case AARCH64_OPND_ADDR_SIMM10: case AARCH64_OPND_ADDR_UIMM12: + case AARCH64_OPND_ADDR_SIMM11: + case AARCH64_OPND_ADDR_SIMM13: /* Immediate offset in an address. */ insn = get_aarch64_insn (buf); -- cgit v1.1