From c76820a017db5f7267d3e86851af41dd8adcbebf Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Fri, 3 Nov 2023 10:03:36 +0100 Subject: RISC-V: reduce redundancy in load/store macro insn handling Within the groups L{B,BU,H,HU,W,WU,D}, S{B,H,W,D}, FL{H,W,D,Q}, and FS{H,W,D,Q} the sole difference between the handling is the insn mnemonic passed to the common handling functions. The intended mnemonic, however, can easily be retrieved. Furthermore leverags that Sx and FSx are then handled identically, too, and hence their cases can also be folded. --- gas/config/tc-riscv.c | 91 ++++----------------------------------------------- 1 file changed, 6 insertions(+), 85 deletions(-) (limited to 'gas/config') diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index aa952a6..30e14bb 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2056,88 +2056,18 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr, BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); break; - case M_LB: - pcrel_load (rd, rd, imm_expr, "lb", + case M_Lx: + pcrel_load (rd, rd, imm_expr, ip->insn_mo->name, BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); break; - case M_LBU: - pcrel_load (rd, rd, imm_expr, "lbu", + case M_FLx: + pcrel_load (rd, rs1, imm_expr, ip->insn_mo->name, BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); break; - case M_LH: - pcrel_load (rd, rd, imm_expr, "lh", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); - break; - - case M_LHU: - pcrel_load (rd, rd, imm_expr, "lhu", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); - break; - - case M_LW: - pcrel_load (rd, rd, imm_expr, "lw", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); - break; - - case M_LWU: - pcrel_load (rd, rd, imm_expr, "lwu", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); - break; - - case M_LD: - pcrel_load (rd, rd, imm_expr, "ld", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); - break; - - case M_FLW: - pcrel_load (rd, rs1, imm_expr, "flw", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); - break; - - case M_FLD: - pcrel_load (rd, rs1, imm_expr, "fld", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); - break; - - case M_FLQ: - pcrel_load (rd, rs1, imm_expr, "flq", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); - break; - - case M_SB: - pcrel_store (rs2, rs1, imm_expr, "sb", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); - break; - - case M_SH: - pcrel_store (rs2, rs1, imm_expr, "sh", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); - break; - - case M_SW: - pcrel_store (rs2, rs1, imm_expr, "sw", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); - break; - - case M_SD: - pcrel_store (rs2, rs1, imm_expr, "sd", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); - break; - - case M_FSW: - pcrel_store (rs2, rs1, imm_expr, "fsw", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); - break; - - case M_FSD: - pcrel_store (rs2, rs1, imm_expr, "fsd", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); - break; - - case M_FSQ: - pcrel_store (rs2, rs1, imm_expr, "fsq", + case M_Sx_FSx: + pcrel_store (rs2, rs1, imm_expr, ip->insn_mo->name, BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); break; @@ -2165,15 +2095,6 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr, vector_macro (ip); break; - case M_FLH: - pcrel_load (rd, rs1, imm_expr, "flh", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); - break; - case M_FSH: - pcrel_store (rs2, rs1, imm_expr, "fsh", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); - break; - default: as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name); break; -- cgit v1.1