From a8eb42a8b7d48ff6bd12ac83b0e31967b4f5abf1 Mon Sep 17 00:00:00 2001 From: Alan Modra Date: Wed, 11 Apr 2018 18:46:05 +0930 Subject: Remove i860, i960, bout and aout-adobe targets Plus remove a few leftovers from the 29k support. include/ * aout/adobe.h: Delete. * aout/reloc.h: Delete. * coff/i860.h: Delete. * coff/i960.h: Delete. * elf/i860.h: Delete. * elf/i960.h: Delete. * opcode/i860.h: Delete. * opcode/i960.h: Delete. * aout/aout64.h (enum reloc_type): Trim off 29k and other unused values. * aout/ar.h (ARMAGB): Remove. * coff/internal.h (struct internal_aouthdr, struct internal_scnhdr, union internal_auxent): Remove i960 support. bfd/ * aout-adobe.c: Delete. * bout.c: Delete. * coff-i860.c: Delete. * coff-i960.c: Delete. * cpu-i860.c: Delete. * cpu-i960.c: Delete. * elf32-i860.c: Delete. * elf32-i960.c: Delete. * hosts/i860mach3.h: Delete. * Makefile.am: Remove i860, i960, bout, and adobe support. * archures.c: Remove i860 and i960 support. * coffcode.h: Likewise. * reloc.c: Likewise. * aoutx.h: Comment updates. * archive.c: Remove BOUT and i960 support. * bfd.c: Remove BOUT support. * coffswap.h: Remove i960 support. * config.bfd: Remove i860, i960 and adobe targets. * configure.ac: Remove adode, bout, i860, i960, icoff targets. * targets.c: Likewise. * ieee.c: Remove i960 support. * mach-o.c: Remove i860 support. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. * po/SRC-POTFILES.in: Regenerate. opcodes/ * opcodes/i860-dis.c: Delete. * opcodes/i960-dis.c: Delete. * Makefile.am: Remove i860 and i960 support. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. binutils/ * ieee.c: Remove i960 support. * od-macho.c: Remove i860 support. * readelf.c: Remove i860 and i960 support. * testsuite/binutils-all/objcopy.exp: Likewise. * testsuite/binutils-all/objdump.exp: Likewise. * testsuite/lib/binutils-common.exp: Likewise. gas/ * config/aout_gnu.h: Delete. * config/tc-i860.c: Delete. * config/tc-i860.h: Delete. * config/tc-i960.c: Delete. * config/tc-i960.h: Delete. * doc/c-i860.texi: Delete. * doc/c-i960.texi: Delete. * testsuite/gas/i860/README.i860: Delete. * testsuite/gas/i860/bitwise.d: Delete. * testsuite/gas/i860/bitwise.s: Delete. * testsuite/gas/i860/branch.d: Delete. * testsuite/gas/i860/branch.s: Delete. * testsuite/gas/i860/bte.d: Delete. * testsuite/gas/i860/bte.s: Delete. * testsuite/gas/i860/dir-align01.d: Delete. * testsuite/gas/i860/dir-align01.s: Delete. * testsuite/gas/i860/dir-intel01.d: Delete. * testsuite/gas/i860/dir-intel01.s: Delete. * testsuite/gas/i860/dir-intel02.d: Delete. * testsuite/gas/i860/dir-intel02.s: Delete. * testsuite/gas/i860/dir-intel03-err.l: Delete. * testsuite/gas/i860/dir-intel03-err.s: Delete. * testsuite/gas/i860/dual01.d: Delete. * testsuite/gas/i860/dual01.s: Delete. * testsuite/gas/i860/dual02-err.l: Delete. * testsuite/gas/i860/dual02-err.s: Delete. * testsuite/gas/i860/dual03.d: Delete. * testsuite/gas/i860/dual03.s: Delete. * testsuite/gas/i860/fldst01.d: Delete. * testsuite/gas/i860/fldst01.s: Delete. * testsuite/gas/i860/fldst02.d: Delete. * testsuite/gas/i860/fldst02.s: Delete. * testsuite/gas/i860/fldst03.d: Delete. * testsuite/gas/i860/fldst03.s: Delete. * testsuite/gas/i860/fldst04.d: Delete. * testsuite/gas/i860/fldst04.s: Delete. * testsuite/gas/i860/fldst05.d: Delete. * testsuite/gas/i860/fldst05.s: Delete. * testsuite/gas/i860/fldst06.d: Delete. * testsuite/gas/i860/fldst06.s: Delete. * testsuite/gas/i860/fldst07.d: Delete. * testsuite/gas/i860/fldst07.s: Delete. * testsuite/gas/i860/fldst08.d: Delete. * testsuite/gas/i860/fldst08.s: Delete. * testsuite/gas/i860/float01.d: Delete. * testsuite/gas/i860/float01.s: Delete. * testsuite/gas/i860/float02.d: Delete. * testsuite/gas/i860/float02.s: Delete. * testsuite/gas/i860/float03.d: Delete. * testsuite/gas/i860/float03.s: Delete. * testsuite/gas/i860/float04.d: Delete. * testsuite/gas/i860/float04.s: Delete. * testsuite/gas/i860/form.d: Delete. * testsuite/gas/i860/form.s: Delete. * testsuite/gas/i860/i860.exp: Delete. * testsuite/gas/i860/iarith.d: Delete. * testsuite/gas/i860/iarith.s: Delete. * testsuite/gas/i860/ldst01.d: Delete. * testsuite/gas/i860/ldst01.s: Delete. * testsuite/gas/i860/ldst02.d: Delete. * testsuite/gas/i860/ldst02.s: Delete. * testsuite/gas/i860/ldst03.d: Delete. * testsuite/gas/i860/ldst03.s: Delete. * testsuite/gas/i860/ldst04.d: Delete. * testsuite/gas/i860/ldst04.s: Delete. * testsuite/gas/i860/ldst05.d: Delete. * testsuite/gas/i860/ldst05.s: Delete. * testsuite/gas/i860/ldst06.d: Delete. * testsuite/gas/i860/ldst06.s: Delete. * testsuite/gas/i860/pfam.d: Delete. * testsuite/gas/i860/pfam.s: Delete. * testsuite/gas/i860/pfmam.d: Delete. * testsuite/gas/i860/pfmam.s: Delete. * testsuite/gas/i860/pfmsm.d: Delete. * testsuite/gas/i860/pfmsm.s: Delete. * testsuite/gas/i860/pfsm.d: Delete. * testsuite/gas/i860/pfsm.s: Delete. * testsuite/gas/i860/pseudo-ops01.d: Delete. * testsuite/gas/i860/pseudo-ops01.s: Delete. * testsuite/gas/i860/regress01.d: Delete. * testsuite/gas/i860/regress01.s: Delete. * testsuite/gas/i860/shift.d: Delete. * testsuite/gas/i860/shift.s: Delete. * testsuite/gas/i860/simd.d: Delete. * testsuite/gas/i860/simd.s: Delete. * testsuite/gas/i860/system.d: Delete. * testsuite/gas/i860/system.s: Delete. * testsuite/gas/i860/xp.d: Delete. * testsuite/gas/i860/xp.s: Delete. * Makefile.am: Remove i860 and i960 support. * configure.tgt: Likewise. * doc/Makefile.am: Likewise. * doc/all.texi: Likewise. * testsuite/gas/all/gas.exp * config/obj-coff.h: Remove i960 support. * doc/internals.texi: Likewise. * expr.c: Likewise. * read.c: Likewise. * write.c: Likewise. * write.h: Likewise. * testsuite/gas/lns/lns.exp: Likewise. * testsuite/gas/symver/symver.exp: Likewise. * config/tc-m68k.c: Remove BOUT support. * config/tc-score.c: Likewise. * config/tc-score7.c: Likewise. * config/tc-sparc.c: Likewise. * symbols.c: Likewise. * doc/h8.texi: Likewise. * configure.ac: Remove BOUT and i860 support. * doc/as.texinfo: Remove BOUT, i860 and i960 support * Makefile.in: Regenerate. * config.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. ld/ * emulparams/coff_i860.sh: Delete. * emulparams/elf32_i860.sh: Delete. * emulparams/elf32_i960.sh: Delete. * emulparams/gld960.sh: Delete. * emulparams/gld960coff.sh: Delete. * emulparams/lnk960.sh: Delete. * emultempl/gld960.em: Delete. * emultempl/gld960c.em: Delete. * emultempl/lnk960.em: Delete. * scripttempl/i860coff.sc: Delete. * scripttempl/i960.sc: Delete. * ld.texinfo: Remove i960 support. * Makefile.am: Remove i860 and i960 support. * configure.tgt: Likewise. * testsuite/ld-discard/extern.d: Likewise. * testsuite/ld-discard/start.d: Likewise. * testsuite/ld-discard/static.d: Likewise. * testsuite/ld-elf/compressed1d.d: Likewise. * testsuite/ld-elf/group1.d: Likewise. * testsuite/ld-elf/group3b.d: Likewise. * testsuite/ld-elf/group8a.d: Likewise. * testsuite/ld-elf/group8b.d: Likewise. * testsuite/ld-elf/group9a.d: Likewise. * testsuite/ld-elf/group9b.d: Likewise. * testsuite/ld-elf/linkonce2.d: Likewise. * testsuite/ld-elf/merge.d: Likewise. * testsuite/ld-elf/merge2.d: Likewise. * testsuite/ld-elf/merge3.d: Likewise. * testsuite/ld-elf/orphan-10.d: Likewise. * testsuite/ld-elf/orphan-11.d: Likewise. * testsuite/ld-elf/orphan-12.d: Likewise. * testsuite/ld-elf/orphan-9.d: Likewise. * testsuite/ld-elf/orphan-region.d: Likewise. * testsuite/ld-elf/orphan.d: Likewise. * testsuite/ld-elf/orphan3.d: Likewise. * testsuite/ld-elf/pr12851.d: Likewise. * testsuite/ld-elf/pr12975.d: Likewise. * testsuite/ld-elf/pr13177.d: Likewise. * testsuite/ld-elf/pr13195.d: Likewise. * testsuite/ld-elf/pr17550a.d: Likewise. * testsuite/ld-elf/pr17550b.d: Likewise. * testsuite/ld-elf/pr17550c.d: Likewise. * testsuite/ld-elf/pr17550d.d: Likewise. * testsuite/ld-elf/pr17615.d: Likewise. * testsuite/ld-elf/pr20528a.d: Likewise. * testsuite/ld-elf/pr20528b.d: Likewise. * testsuite/ld-elf/pr21562a.d: Likewise. * testsuite/ld-elf/pr21562b.d: Likewise. * testsuite/ld-elf/pr21562c.d: Likewise. * testsuite/ld-elf/pr21562d.d: Likewise. * testsuite/ld-elf/pr21562i.d: Likewise. * testsuite/ld-elf/pr21562j.d: Likewise. * testsuite/ld-elf/pr21562k.d: Likewise. * testsuite/ld-elf/pr21562l.d: Likewise. * testsuite/ld-elf/pr21562m.d: Likewise. * testsuite/ld-elf/pr21562n.d: Likewise. * testsuite/ld-elf/pr22677.d: Likewise. * testsuite/ld-elf/pr22836-1a.d: Likewise. * testsuite/ld-elf/pr22836-1b.d: Likewise. * testsuite/ld-elf/pr349.d: Likewise. * testsuite/ld-elf/sec-to-seg.exp: Likewise. * testsuite/ld-elf/sec64k.exp: Likewise. * testsuite/ld-elf/warn1.d: Likewise. * testsuite/ld-elf/warn2.d: Likewise. * testsuite/ld-elf/warn3.d: Likewise. * testsuite/lib/ld-lib.exp: Likewise. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. --- gas/config/aout_gnu.h | 451 -------- gas/config/obj-coff.h | 38 +- gas/config/tc-i860.c | 1491 --------------------------- gas/config/tc-i860.h | 95 -- gas/config/tc-i960.c | 2667 ------------------------------------------------ gas/config/tc-i960.h | 185 ---- gas/config/tc-m68k.c | 4 +- gas/config/tc-score.c | 3 +- gas/config/tc-score7.c | 3 +- gas/config/tc-sparc.c | 4 - 10 files changed, 5 insertions(+), 4936 deletions(-) delete mode 100644 gas/config/aout_gnu.h delete mode 100644 gas/config/tc-i860.c delete mode 100644 gas/config/tc-i860.h delete mode 100644 gas/config/tc-i960.c delete mode 100644 gas/config/tc-i960.h (limited to 'gas/config') diff --git a/gas/config/aout_gnu.h b/gas/config/aout_gnu.h deleted file mode 100644 index f404d1e..0000000 --- a/gas/config/aout_gnu.h +++ /dev/null @@ -1,451 +0,0 @@ -/* This file is aout_gnu.h - - Copyright (C) 1987-2018 Free Software Foundation, Inc. - - This file is part of GAS, the GNU Assembler. - - GAS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GAS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS; see the file COPYING. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -#ifndef __A_OUT_GNU_H__ -#define __A_OUT_GNU_H__ - -/* There are two main flavours of a.out, one which uses the standard - relocations, and one which uses extended relocations. - - Today, the extended reloc uses are - TC_SPARC - - each must define the enum reloc_type - -*/ - -#if defined(TC_SPARC) -enum reloc_type - { - RELOC_8, RELOC_16, RELOC_32,/* simple relocations */ - RELOC_DISP8, RELOC_DISP16, RELOC_DISP32, /* pc-rel displacement */ - RELOC_WDISP30, RELOC_WDISP22, - RELOC_HI22, RELOC_22, - RELOC_13, RELOC_LO10, - RELOC_SFA_BASE, RELOC_SFA_OFF13, - RELOC_BASE10, RELOC_BASE13, RELOC_BASE22, /* P.I.C. (base-relative) */ - RELOC_PC10, RELOC_PC22, /* for some sort of pc-rel P.I.C. (?) */ - RELOC_JMP_TBL, /* P.I.C. jump table */ - RELOC_SEGOFF16, /* reputedly for shared libraries somehow */ - RELOC_GLOB_DAT, RELOC_JMP_SLOT, RELOC_RELATIVE, - RELOC_10, RELOC_11, - RELOC_WDISP2_14, - RELOC_WDISP19, - RELOC_HHI22, - RELOC_HLO10, - - /* 29K relocation types */ - RELOC_JUMPTARG, RELOC_CONST, RELOC_CONSTH, - - RELOC_WDISP14, RELOC_WDISP21, - - NO_RELOC - }; - -#define USE_EXTENDED_RELOC 1 -#else -#define USE_EXTENDED_RELOC 0 -#endif /* TC_SPARC */ - -#define __GNU_EXEC_MACROS__ - -#ifndef __STRUCT_EXEC_OVERRIDE__ - -/* This is the layout on disk of a Unix V7, Berkeley, SunOS, Vax Ultrix - "struct exec". Don't assume that on this machine, the "struct exec" - will lay out the same sizes or alignments. */ - -struct exec_bytes - { - unsigned char a_info[4]; - unsigned char a_text[4]; - unsigned char a_data[4]; - unsigned char a_bss[4]; - unsigned char a_syms[4]; - unsigned char a_entry[4]; - unsigned char a_trsize[4]; - unsigned char a_drsize[4]; - }; - -/* How big the "struct exec" is on disk */ -#define EXEC_BYTES_SIZE (8 * 4) - -/* This is the layout in memory of a "struct exec" while we process it. */ - -struct exec -{ - unsigned long a_info; /* Use macros N_MAGIC, etc for access */ - unsigned a_text; /* length of text, in bytes */ - unsigned a_data; /* length of data, in bytes */ - unsigned a_bss; /* length of uninitialized data area for file, in bytes */ - unsigned a_syms; /* length of symbol table data in file, in bytes */ - unsigned a_entry; /* start address */ - unsigned a_trsize; /* length of relocation info for text, in bytes */ - unsigned a_drsize; /* length of relocation info for data, in bytes */ -}; - -#endif /* __STRUCT_EXEC_OVERRIDE__ */ - -/* these go in the N_MACHTYPE field */ -/* These symbols could be defined by code from Suns...punt 'em */ -#undef M_UNKNOWN -#undef M_68010 -#undef M_68020 -#undef M_SPARC -enum machine_type - { - M_UNKNOWN = 0, - M_68010 = 1, - M_68020 = 2, - M_SPARC = 3, - /* skip a bunch so we don't run into any of sun's numbers */ - M_386 = 100, - M_29K = 101, - M_RS6000 = 102, /* IBM RS/6000 */ - M_VAX4K_NETBSD = 150, - /* HP/BSD formats */ - M_HP200 = 200, /* hp200 (68010) BSD binary */ - M_HP300 = 300, /* hp300 (68020+68881) BSD binary */ - M_HPUX23 = 0x020C /* hp200/300 HPUX binary */ - }; - -#define N_MAGIC(execp) ((execp)->a_info & 0xffff) -#define N_MACHTYPE(execp) ((enum machine_type)(((execp)->a_info >> 16) & 0xff)) -#define N_FLAGS(execp) (((execp)->a_info >> 24) & 0xff) -#define N_SET_INFO(execp, magic, type, flags) \ - ((execp)->a_info = ((magic) & 0xffff) \ - | (((int)(type) & 0xff) << 16) \ - | (((flags) & 0xff) << 24)) -#define N_SET_MAGIC(execp, magic) \ - ((execp)->a_info = (((execp)->a_info & 0xffff0000) | ((magic) & 0xffff))) - -#define N_SET_MACHTYPE(execp, machtype) \ - ((execp)->a_info = \ - ((execp)->a_info & 0xff00ffff) | ((((int) (machtype)) & 0xff) << 16)) - -#define N_SET_FLAGS(execp, flags) \ - ((execp)->a_info = \ - ((execp)->a_info & 0x00ffffff) | (((flags) & 0xff) << 24)) - -/* Code indicating object file or impure executable. */ -#ifndef OMAGIC -#define OMAGIC 0407 -#endif -/* Code indicating pure executable. */ -#define NMAGIC 0410 -/* Code indicating demand-paged executable. */ -#define ZMAGIC 0413 - -/* Virtual Address of text segment from the a.out file. For OMAGIC, - (almost always "unlinked .o's" these days), should be zero. - For linked files, should reflect reality if we know it. */ - -#ifndef N_TXTADDR -#define N_TXTADDR(x) (N_MAGIC(x)==OMAGIC? 0 : TEXT_START_ADDR) -#endif - -#ifndef N_BADMAG -#define N_BADMAG(x) (N_MAGIC(x) != OMAGIC \ - && N_MAGIC(x) != NMAGIC \ - && N_MAGIC(x) != ZMAGIC) -#endif - -/* By default, segment size is constant. But on some machines, it can - be a function of the a.out header (e.g. machine type). */ -#ifndef N_SEGSIZE -#define N_SEGSIZE(x) SEGMENT_SIZE -#endif - -/* This complexity is for encapsulated COFF support */ -#ifndef _N_HDROFF -#define _N_HDROFF(x) (N_SEGSIZE(x) - sizeof (struct exec)) -#endif - -#ifndef N_TXTOFF -#define N_TXTOFF(x) (N_MAGIC(x) == ZMAGIC ? \ - _N_HDROFF((x)) + sizeof (struct exec) : \ - sizeof (struct exec)) -#endif - -#ifndef N_DATOFF -#define N_DATOFF(x) ( N_TXTOFF(x) + (x)->a_text ) -#endif - -#ifndef N_TRELOFF -#define N_TRELOFF(x) ( N_DATOFF(x) + (x)->a_data ) -#endif - -#ifndef N_DRELOFF -#define N_DRELOFF(x) ( N_TRELOFF(x) + (x)->a_trsize ) -#endif - -#ifndef N_SYMOFF -#define N_SYMOFF(x) ( N_DRELOFF(x) + (x)->a_drsize ) -#endif - -#ifndef N_STROFF -#define N_STROFF(x) ( N_SYMOFF(x) + (x)->a_syms ) -#endif - -/* Address of text segment in memory after it is loaded. */ -#ifndef N_TXTADDR -#define N_TXTADDR(x) 0 -#endif - -#ifndef N_DATADDR -#define N_DATADDR(x) \ - (N_MAGIC(x)==OMAGIC? (N_TXTADDR(x)+(x)->a_text) \ - : (N_SEGSIZE(x) + ((N_TXTADDR(x)+(x)->a_text-1) & ~(N_SEGSIZE(x)-1)))) -#endif - -/* Address of bss segment in memory after it is loaded. */ -#define N_BSSADDR(x) (N_DATADDR(x) + (x)->a_data) - -struct nlist - { - union - { - char *n_name; - struct nlist *n_next; - long n_strx; - } - n_un; - unsigned char n_type; - char n_other; - short n_desc; - unsigned long n_value; - }; - -#define N_UNDF 0 -#define N_ABS 2 -#define N_TEXT 4 -#define N_DATA 6 -#define N_BSS 8 -#define N_COMM 0x12 /* common (visible in shared lib commons) */ -#define N_FN 0x1F /* File name of a .o file */ - -/* Note: N_EXT can only usefully be OR-ed with N_UNDF, N_ABS, N_TEXT, - N_DATA, or N_BSS. When the low-order bit of other types is set, - (e.g. N_WARNING versus N_FN), they are two different types. */ -#define N_EXT 1 -#define N_TYPE 036 -#define N_STAB 0340 - -/* The following type indicates the definition of a symbol as being - an indirect reference to another symbol. The other symbol - appears as an undefined reference, immediately following this symbol. - - Indirection is asymmetrical. The other symbol's value will be used - to satisfy requests for the indirect symbol, but not vice versa. - If the other symbol does not have a definition, libraries will - be searched to find a definition. */ - -#define N_INDR 0xa - -/* The following symbols refer to set elements. - All the N_SET[ATDB] symbols with the same name form one set. - Space is allocated for the set in the text section, and each set - element's value is stored into one word of the space. - The first word of the space is the length of the set (number of elements). - - The address of the set is made into an N_SETV symbol - whose name is the same as the name of the set. - This symbol acts like a N_DATA global symbol - in that it can satisfy undefined external references. */ - -/* These appear as input to LD, in a .o file. */ -#define N_SETA 0x14 /* Absolute set element symbol */ -#define N_SETT 0x16 /* Text set element symbol */ -#define N_SETD 0x18 /* Data set element symbol */ -#define N_SETB 0x1A /* Bss set element symbol */ - -/* This is output from LD. */ -#define N_SETV 0x1C /* Pointer to set vector in data area. */ - -/* Warning symbol. The text gives a warning message, the next symbol - in the table will be undefined. When the symbol is referenced, the - message is printed. */ - -#define N_WARNING 0x1e - -/* Weak symbols. These are a GNU extension to the a.out format. The - semantics are those of ELF weak symbols. Weak symbols are always - externally visible. The N_WEAK? values are squeezed into the - available slots. The value of a N_WEAKU symbol is 0. The values - of the other types are the definitions. */ -#define N_WEAKU 0x0d /* Weak undefined symbol. */ -#define N_WEAKA 0x0e /* Weak absolute symbol. */ -#define N_WEAKT 0x0f /* Weak text symbol. */ -#define N_WEAKD 0x10 /* Weak data symbol. */ -#define N_WEAKB 0x11 /* Weak bss symbol. */ - -/* This structure describes a single relocation to be performed. - The text-relocation section of the file is a vector of these structures, - all of which apply to the text section. - Likewise, the data-relocation section applies to the data section. */ - -/* The following enum and struct were borrowed from SunOS's - /usr/include/sun4/a.out.h and extended to handle - other machines. It is currently used on SPARC. - - reloc_ext_bytes is how it looks on disk. reloc_info_extended is - how we might process it on a native host. */ -#if USE_EXTENDED_RELOC - -struct reloc_ext_bytes - { - unsigned char r_address[4]; - unsigned char r_index[3]; - unsigned char r_bits[1]; - unsigned char r_addend[4]; - }; - -#define RELOC_EXT_BITS_EXTERN_BIG 0x80 -#define RELOC_EXT_BITS_EXTERN_LITTLE 0x01 - -#define RELOC_EXT_BITS_TYPE_BIG 0x1F -#define RELOC_EXT_BITS_TYPE_SH_BIG 0 -#define RELOC_EXT_BITS_TYPE_LITTLE 0xF8 -#define RELOC_EXT_BITS_TYPE_SH_LITTLE 3 - -#define RELOC_EXT_SIZE 12 /* Bytes per relocation entry */ - -struct reloc_info_extended -{ - unsigned long r_address; - unsigned int r_index:24; -# define r_symbolnum r_index - unsigned r_extern:1; - unsigned:2; - /* RS/6000 compiler does not support enum bitfield - enum reloc_type r_type:5; */ - enum reloc_type r_type; - long int r_addend; -}; - -#else - -/* The standard, old-fashioned, Berkeley compatible relocation struct */ - -#ifdef TC_I860 -/* NOTE: three bits max, see struct reloc_info_i860.r_type */ -enum i860_reloc_type - { - NO_RELOC = 0, BRADDR, LOW0, LOW1, LOW2, LOW3, LOW4, SPLIT0, SPLIT1, SPLIT2, RELOC_32, - }; - -typedef enum i860_reloc_type reloc_type; - -/* NOTE: two bits max, see reloc_info_i860.r_type */ -enum highlow_type - { - NO_SPEC = 0, PAIR, HIGH, HIGHADJ, - }; - -struct reloc_info_i860 -{ - unsigned long r_address; - /* - * Using bit fields here is a bad idea because the order is not portable. :-( - */ - unsigned int r_symbolnum:24; - unsigned int r_pcrel:1; - unsigned int r_extern:1; - /* combining the two field simplifies the argument passing in "new_fix()" */ - /* and is compatible with the existing Sparc #ifdef's */ - /* r_type: highlow_type - bits 5,4; reloc_type - bits 3-0 */ - unsigned int r_type:6; - long r_addend; -}; - -#endif /* TC_I860 */ - -struct reloc_std_bytes - { - unsigned char r_address[4]; - unsigned char r_index[3]; - unsigned char r_bits[1]; - }; - -#define RELOC_STD_BITS_PCREL_BIG 0x80 -#define RELOC_STD_BITS_PCREL_LITTLE 0x01 - -#define RELOC_STD_BITS_LENGTH_BIG 0x60 -#define RELOC_STD_BITS_LENGTH_SH_BIG 5 /* To shift to units place */ -#define RELOC_STD_BITS_LENGTH_LITTLE 0x06 -#define RELOC_STD_BITS_LENGTH_SH_LITTLE 1 - -#define RELOC_STD_BITS_EXTERN_BIG 0x10 -#define RELOC_STD_BITS_EXTERN_LITTLE 0x08 - -#define RELOC_STD_BITS_BASEREL_BIG 0x08 -#define RELOC_STD_BITS_BASEREL_LITTLE 0x08 - -#define RELOC_STD_BITS_JMPTABLE_BIG 0x04 -#define RELOC_STD_BITS_JMPTABLE_LITTLE 0x04 - -#define RELOC_STD_BITS_RELATIVE_BIG 0x02 -#define RELOC_STD_BITS_RELATIVE_LITTLE 0x02 - -#define RELOC_STD_SIZE 8 /* Bytes per relocation entry */ - -#endif /* USE_EXTENDED_RELOC */ - -#ifndef CUSTOM_RELOC_FORMAT -struct relocation_info -{ - /* Address (within segment) to be relocated. */ - int r_address; - /* The meaning of r_symbolnum depends on r_extern. */ - unsigned int r_symbolnum:24; - /* Nonzero means value is a pc-relative offset - and it should be relocated for changes in its own address - as well as for changes in the symbol or section specified. */ - unsigned int r_pcrel:1; - /* Length (as exponent of 2) of the field to be relocated. - Thus, a value of 2 indicates 1<<2 bytes. */ - unsigned int r_length:2; - /* 1 => relocate with value of symbol. - r_symbolnum is the index of the symbol - in file's the symbol table. - 0 => relocate with the address of a segment. - r_symbolnum is N_TEXT, N_DATA, N_BSS or N_ABS - (the N_EXT bit may be set also, but signifies nothing). */ - unsigned int r_extern:1; - /* The next three bits are for SunOS shared libraries, and seem to - be undocumented. */ -#ifdef TC_NS32K - unsigned int r_bsr:1; - unsigned int r_disp:2; -#else - unsigned int r_baserel:1; /* Linkage table relative */ - unsigned int r_jmptable:1; /* pc-relative to jump table */ - unsigned int r_relative:1; /* "relative relocation" */ -#endif /* TC_NS32K */ - /* unused */ - unsigned int r_pad:1; /* Padding -- set to zero */ -}; - -#endif /* CUSTOM_RELOC_FORMAT */ - -#endif /* __A_OUT_GNU_H__ */ - -/* end of aout_gnu.h */ diff --git a/gas/config/obj-coff.h b/gas/config/obj-coff.h index 7c4fff5..ee28ab4 100644 --- a/gas/config/obj-coff.h +++ b/gas/config/obj-coff.h @@ -75,11 +75,6 @@ #endif #endif -#ifdef TC_I960 -#include "coff/i960.h" -#define TARGET_FORMAT "coff-Intel-little" -#endif - #ifdef TC_Z80 #include "coff/z80.h" #define TARGET_FORMAT "coff-z80" @@ -168,11 +163,6 @@ /* Alter the field names, for now, until we've fixed up the other references to use the new name. */ -#ifdef TC_I960 -#define TC_SYMFIELD_TYPE symbolS * -#define sy_tc bal -#endif - #define OBJ_SYMFIELD_TYPE unsigned long #define sy_obj sy_obj_flags @@ -224,17 +214,7 @@ /* Internal use only definitions. SF_ stands for symbol flags. - These values can be assigned to sy_symbol.ost_flags field of a symbolS. - - You'll break i960 if you shift the SYSPROC bits anywhere else. for - more on the balname/callname hack, see tc-i960.h. b.out is done - differently. */ - -#define SF_I960_MASK 0x000001ff /* Bits 0-8 are used by the i960 port. */ -#define SF_SYSPROC 0x0000003f /* bits 0-5 are used to store the sysproc number. */ -#define SF_IS_SYSPROC 0x00000040 /* bit 6 marks symbols that are sysprocs. */ -#define SF_BALNAME 0x00000080 /* bit 7 marks BALNAME symbols. */ -#define SF_CALLNAME 0x00000100 /* bit 8 marks CALLNAME symbols. */ + These values can be assigned to sy_symbol.ost_flags field of a symbolS. */ #define SF_NORMAL_MASK 0x0000ffff /* bits 12-15 are general purpose. */ @@ -269,11 +249,6 @@ #define SF_GET_TAGGED(s) (SF_GET (s) & SF_TAGGED) #define SF_GET_TAG(s) (SF_GET (s) & SF_TAG) #define SF_GET_GET_SEGMENT(s) (SF_GET (s) & SF_GET_SEGMENT) -#define SF_GET_I960(s) (SF_GET (s) & SF_I960_MASK) /* Used by i960. */ -#define SF_GET_BALNAME(s) (SF_GET (s) & SF_BALNAME) /* Used by i960. */ -#define SF_GET_CALLNAME(s) (SF_GET (s) & SF_CALLNAME) /* Used by i960. */ -#define SF_GET_IS_SYSPROC(s) (SF_GET (s) & SF_IS_SYSPROC) /* Used by i960. */ -#define SF_GET_SYSPROC(s) (SF_GET (s) & SF_SYSPROC) /* Used by i960. */ /* Modifiers. */ #define SF_SET(s,v) (SF_GET (s) = (v)) @@ -290,11 +265,6 @@ #define SF_SET_TAGGED(s) (SF_GET (s) |= SF_TAGGED) #define SF_SET_TAG(s) (SF_GET (s) |= SF_TAG) #define SF_SET_GET_SEGMENT(s) (SF_GET (s) |= SF_GET_SEGMENT) -#define SF_SET_I960(s,v) (SF_GET (s) |= ((v) & SF_I960_MASK)) /* Used by i960. */ -#define SF_SET_BALNAME(s) (SF_GET (s) |= SF_BALNAME) /* Used by i960. */ -#define SF_SET_CALLNAME(s) (SF_GET (s) |= SF_CALLNAME) /* Used by i960. */ -#define SF_SET_IS_SYSPROC(s) (SF_GET (s) |= SF_IS_SYSPROC) /* Used by i960. */ -#define SF_SET_SYSPROC(s,v) (SF_GET (s) |= ((v) & SF_SYSPROC)) /* Used by i960. */ /* Line number handling. */ @@ -330,12 +300,6 @@ extern symbolS *coff_last_function; /* Sanity check. */ -#ifdef TC_I960 -#ifndef C_LEAFSTAT -hey ! Where is the C_LEAFSTAT definition ? i960 - coff support is depending on it. -#endif /* no C_LEAFSTAT */ -#endif /* TC_I960 */ - extern const pseudo_typeS coff_pseudo_table[]; #ifndef obj_pop_insert diff --git a/gas/config/tc-i860.c b/gas/config/tc-i860.c deleted file mode 100644 index 5872678..0000000 --- a/gas/config/tc-i860.c +++ /dev/null @@ -1,1491 +0,0 @@ -/* tc-i860.c -- Assembler for the Intel i860 architecture. - Copyright (C) 1989-2018 Free Software Foundation, Inc. - - Brought back from the dead and completely reworked - by Jason Eckhardt . - - This file is part of GAS, the GNU Assembler. - - GAS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GAS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License along - with GAS; see the file COPYING. If not, write to the Free Software - Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#include "as.h" -#include "safe-ctype.h" -#include "subsegs.h" -#include "opcode/i860.h" -#include "elf/i860.h" - - -/* The opcode hash table. */ -static struct hash_control *op_hash = NULL; - -/* These characters always start a comment. */ -const char comment_chars[] = "#!/"; - -/* These characters start a comment at the beginning of a line. */ -const char line_comment_chars[] = "#/"; - -const char line_separator_chars[] = ";"; - -/* Characters that can be used to separate the mantissa from the exponent - in floating point numbers. */ -const char EXP_CHARS[] = "eE"; - -/* Characters that indicate this number is a floating point constant. - As in 0f12.456 or 0d1.2345e12. */ -const char FLT_CHARS[] = "rRsSfFdDxXpP"; - -/* Register prefix (depends on syntax). */ -static char reg_prefix; - -#define MAX_FIXUPS 2 - -struct i860_it -{ - const char *error; - unsigned long opcode; - enum expand_type expand; - struct i860_fi - { - expressionS exp; - bfd_reloc_code_real_type reloc; - int pcrel; - valueT fup; - } fi[MAX_FIXUPS]; -} the_insn; - -/* The current fixup count. */ -static int fc; - -static char *expr_end; - -/* Indicates error if a pseudo operation was expanded after a branch. */ -static char last_expand; - -/* If true, then warn if any pseudo operations were expanded. */ -static int target_warn_expand = 0; - -/* If true, then XP support is enabled. */ -static int target_xp = 0; - -/* If true, then Intel syntax is enabled (default to AT&T/SVR4 syntax). */ -static int target_intel_syntax = 0; - - -/* Prototypes. */ -static void i860_process_insn (char *); -static void s_dual (int); -static void s_enddual (int); -static void s_atmp (int); -static void s_align_wrapper (int); -static int i860_get_expression (char *); -static bfd_reloc_code_real_type obtain_reloc_for_imm16 (fixS *, long *); -#ifdef DEBUG_I860 -static void print_insn (struct i860_it *); -#endif - -const pseudo_typeS md_pseudo_table[] = -{ - {"align", s_align_wrapper, 0}, - {"dual", s_dual, 0}, - {"enddual", s_enddual, 0}, - {"atmp", s_atmp, 0}, - {NULL, 0, 0}, -}; - -/* Dual-instruction mode handling. */ -enum dual -{ - DUAL_OFF = 0, DUAL_ON, DUAL_DDOT, DUAL_ONDDOT, -}; -static enum dual dual_mode = DUAL_OFF; - -/* Handle ".dual" directive. */ -static void -s_dual (int ignore ATTRIBUTE_UNUSED) -{ - if (target_intel_syntax) - dual_mode = DUAL_ON; - else - as_bad (_("Directive .dual available only with -mintel-syntax option")); -} - -/* Handle ".enddual" directive. */ -static void -s_enddual (int ignore ATTRIBUTE_UNUSED) -{ - if (target_intel_syntax) - dual_mode = DUAL_OFF; - else - as_bad (_("Directive .enddual available only with -mintel-syntax option")); -} - -/* Temporary register used when expanding assembler pseudo operations. */ -static int atmp = 31; - -static void -s_atmp (int ignore ATTRIBUTE_UNUSED) -{ - int temp; - - if (! target_intel_syntax) - { - as_bad (_("Directive .atmp available only with -mintel-syntax option")); - demand_empty_rest_of_line (); - return; - } - - if (strncmp (input_line_pointer, "sp", 2) == 0) - { - input_line_pointer += 2; - atmp = 2; - } - else if (strncmp (input_line_pointer, "fp", 2) == 0) - { - input_line_pointer += 2; - atmp = 3; - } - else if (strncmp (input_line_pointer, "r", 1) == 0) - { - input_line_pointer += 1; - temp = get_absolute_expression (); - if (temp >= 0 && temp <= 31) - atmp = temp; - else - as_bad (_("Unknown temporary pseudo register")); - } - else - { - as_bad (_("Unknown temporary pseudo register")); - } - demand_empty_rest_of_line (); -} - -/* Handle ".align" directive depending on syntax mode. - AT&T/SVR4 syntax uses the standard align directive. However, - the Intel syntax additionally allows keywords for the alignment - parameter: ".align type", where type is one of {.short, .long, - .quad, .single, .double} representing alignments of 2, 4, - 16, 4, and 8, respectively. */ -static void -s_align_wrapper (int arg) -{ - char *parm = input_line_pointer; - - if (target_intel_syntax) - { - /* Replace a keyword with the equivalent integer so the - standard align routine can parse the directive. */ - if (strncmp (parm, ".short", 6) == 0) - strncpy (parm, " 2", 6); - else if (strncmp (parm, ".long", 5) == 0) - strncpy (parm, " 4", 5); - else if (strncmp (parm, ".quad", 5) == 0) - strncpy (parm, " 16", 5); - else if (strncmp (parm, ".single", 7) == 0) - strncpy (parm, " 4", 7); - else if (strncmp (parm, ".double", 7) == 0) - strncpy (parm, " 8", 7); - - while (*input_line_pointer == ' ') - ++input_line_pointer; - } - - s_align_bytes (arg); -} - -/* This function is called once, at assembler startup time. It should - set up all the tables and data structures that the MD part of the - assembler will need. */ -void -md_begin (void) -{ - const char *retval = NULL; - int lose = 0; - unsigned int i = 0; - - op_hash = hash_new (); - - while (i860_opcodes[i].name != NULL) - { - const char *name = i860_opcodes[i].name; - retval = hash_insert (op_hash, name, (void *) &i860_opcodes[i]); - if (retval != NULL) - { - fprintf (stderr, _("internal error: can't hash `%s': %s\n"), - i860_opcodes[i].name, retval); - lose = 1; - } - do - { - if (i860_opcodes[i].match & i860_opcodes[i].lose) - { - fprintf (stderr, - _("internal error: losing opcode: `%s' \"%s\"\n"), - i860_opcodes[i].name, i860_opcodes[i].args); - lose = 1; - } - ++i; - } - while (i860_opcodes[i].name != NULL - && strcmp (i860_opcodes[i].name, name) == 0); - } - - if (lose) - as_fatal (_("Defective assembler. No assembly attempted.")); - - /* Set the register prefix for either Intel or AT&T/SVR4 syntax. */ - reg_prefix = target_intel_syntax ? 0 : '%'; -} - -/* This is the core of the machine-dependent assembler. STR points to a - machine dependent instruction. This function emits the frags/bytes - it assembles to. */ -void -md_assemble (char *str) -{ - char *destp; - int num_opcodes = 1; - int i; - struct i860_it pseudo[3]; - - gas_assert (str); - fc = 0; - - /* Assemble the instruction. */ - i860_process_insn (str); - - /* Check for expandable flag to produce pseudo-instructions. This - is an undesirable feature that should be avoided. */ - if (the_insn.expand != 0 && the_insn.expand != XP_ONLY - && ! (the_insn.fi[0].fup & (OP_SEL_HA | OP_SEL_H | OP_SEL_L | OP_SEL_GOT - | OP_SEL_GOTOFF | OP_SEL_PLT))) - { - for (i = 0; i < 3; i++) - pseudo[i] = the_insn; - - fc = 1; - switch (the_insn.expand) - { - - case E_DELAY: - num_opcodes = 1; - break; - - case E_MOV: - if (the_insn.fi[0].exp.X_add_symbol == NULL - && the_insn.fi[0].exp.X_op_symbol == NULL - && (the_insn.fi[0].exp.X_add_number < (1 << 15) - && the_insn.fi[0].exp.X_add_number >= -(1 << 15))) - break; - - /* Emit "or l%const,r0,ireg_dest". */ - pseudo[0].opcode = (the_insn.opcode & 0x001f0000) | 0xe4000000; - pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_L); - - /* Emit "orh h%const,ireg_dest,ireg_dest". */ - pseudo[1].opcode = (the_insn.opcode & 0x03ffffff) | 0xec000000 - | ((the_insn.opcode & 0x001f0000) << 5); - pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_H); - - num_opcodes = 2; - break; - - case E_ADDR: - if (the_insn.fi[0].exp.X_add_symbol == NULL - && the_insn.fi[0].exp.X_op_symbol == NULL - && (the_insn.fi[0].exp.X_add_number < (1 << 15) - && the_insn.fi[0].exp.X_add_number >= -(1 << 15))) - break; - - /* Emit "orh ha%addr_expr,ireg_src2,r31". */ - pseudo[0].opcode = 0xec000000 | (the_insn.opcode & 0x03e00000) - | (atmp << 16); - pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_HA); - - /* Emit "l%addr_expr(r31),ireg_dest". We pick up the fixup - information from the original instruction. */ - pseudo[1].opcode = (the_insn.opcode & ~0x03e00000) | (atmp << 21); - pseudo[1].fi[0].fup = the_insn.fi[0].fup | OP_SEL_L; - - num_opcodes = 2; - break; - - case E_U32: - if (the_insn.fi[0].exp.X_add_symbol == NULL - && the_insn.fi[0].exp.X_op_symbol == NULL - && (the_insn.fi[0].exp.X_add_number < (1 << 16) - && the_insn.fi[0].exp.X_add_number >= 0)) - break; - - /* Emit "$(opcode)h h%const,ireg_src2,r31". */ - pseudo[0].opcode = (the_insn.opcode & 0xf3e0ffff) | 0x0c000000 - | (atmp << 16); - pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H); - - /* Emit "$(opcode) l%const,r31,ireg_dest". */ - pseudo[1].opcode = (the_insn.opcode & 0xf01f0000) | 0x04000000 - | (atmp << 21); - pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L); - - num_opcodes = 2; - break; - - case E_AND: - if (the_insn.fi[0].exp.X_add_symbol == NULL - && the_insn.fi[0].exp.X_op_symbol == NULL - && (the_insn.fi[0].exp.X_add_number < (1 << 16) - && the_insn.fi[0].exp.X_add_number >= 0)) - break; - - /* Emit "andnot h%const,ireg_src2,r31". */ - pseudo[0].opcode = (the_insn.opcode & 0x03e0ffff) | 0xd4000000 - | (atmp << 16); - pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H); - pseudo[0].fi[0].exp.X_add_number = - -1 - the_insn.fi[0].exp.X_add_number; - - /* Emit "andnot l%const,r31,ireg_dest". */ - pseudo[1].opcode = (the_insn.opcode & 0x001f0000) | 0xd4000000 - | (atmp << 21); - pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L); - pseudo[1].fi[0].exp.X_add_number = - -1 - the_insn.fi[0].exp.X_add_number; - - num_opcodes = 2; - break; - - case E_S32: - if (the_insn.fi[0].exp.X_add_symbol == NULL - && the_insn.fi[0].exp.X_op_symbol == NULL - && (the_insn.fi[0].exp.X_add_number < (1 << 15) - && the_insn.fi[0].exp.X_add_number >= -(1 << 15))) - break; - - /* Emit "orh h%const,r0,r31". */ - pseudo[0].opcode = 0xec000000 | (atmp << 16); - pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H); - - /* Emit "or l%const,r31,r31". */ - pseudo[1].opcode = 0xe4000000 | (atmp << 21) | (atmp << 16); - pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L); - - /* Emit "r31,ireg_src2,ireg_dest". */ - pseudo[2].opcode = (the_insn.opcode & ~0x0400ffff) | (atmp << 11); - pseudo[2].fi[0].fup = OP_IMM_S16; - - num_opcodes = 3; - break; - - default: - as_fatal (_("failed sanity check.")); - } - - the_insn = pseudo[0]; - - /* Warn if an opcode is expanded after a delayed branch. */ - if (num_opcodes > 1 && last_expand == 1) - as_warn (_("Expanded opcode after delayed branch: `%s'"), str); - - /* Warn if an opcode is expanded in dual mode. */ - if (num_opcodes > 1 && dual_mode != DUAL_OFF) - as_warn (_("Expanded opcode in dual mode: `%s'"), str); - - /* Notify if any expansions happen. */ - if (target_warn_expand && num_opcodes > 1) - as_warn (_("An instruction was expanded (%s)"), str); - } - - dwarf2_emit_insn (0); - i = 0; - do - { - int tmp; - - /* Output the opcode. Note that the i860 always reads instructions - as little-endian data. */ - destp = frag_more (4); - number_to_chars_littleendian (destp, the_insn.opcode, 4); - - /* Check for expanded opcode after branch or in dual mode. */ - last_expand = the_insn.fi[0].pcrel; - - /* Output the symbol-dependent stuff. Only btne and bte will ever - loop more than once here, since only they (possibly) have more - than one fixup. */ - for (tmp = 0; tmp < fc; tmp++) - { - if (the_insn.fi[tmp].fup != OP_NONE) - { - fixS *fix; - fix = fix_new_exp (frag_now, - destp - frag_now->fr_literal, - 4, - &the_insn.fi[tmp].exp, - the_insn.fi[tmp].pcrel, - the_insn.fi[tmp].reloc); - - /* Despite the odd name, this is a scratch field. We use - it to encode operand type information. */ - fix->fx_addnumber = the_insn.fi[tmp].fup; - } - } - the_insn = pseudo[++i]; - } - while (--num_opcodes > 0); - -} - -/* Assemble the instruction pointed to by STR. */ -static void -i860_process_insn (char *str) -{ - char *s; - const char *args; - char c; - struct i860_opcode *insn; - char *args_start; - unsigned long opcode; - unsigned int mask; - int match = 0; - int comma = 0; - -#if 1 /* For compiler warnings. */ - args = 0; - insn = 0; - args_start = 0; - opcode = 0; -#endif - - for (s = str; ISLOWER (*s) || *s == '.' || *s == '3' - || *s == '2' || *s == '1'; ++s) - ; - - switch (*s) - { - case '\0': - break; - - case ',': - comma = 1; - - /*FALLTHROUGH*/ - - case ' ': - *s++ = '\0'; - break; - - default: - as_fatal (_("Unknown opcode: `%s'"), str); - } - - /* Check for dual mode ("d.") opcode prefix. */ - if (strncmp (str, "d.", 2) == 0) - { - if (dual_mode == DUAL_ON) - dual_mode = DUAL_ONDDOT; - else - dual_mode = DUAL_DDOT; - str += 2; - } - - if ((insn = (struct i860_opcode *) hash_find (op_hash, str)) == NULL) - { - if (dual_mode == DUAL_DDOT || dual_mode == DUAL_ONDDOT) - str -= 2; - as_bad (_("Unknown opcode: `%s'"), str); - return; - } - - if (comma) - *--s = ','; - - args_start = s; - for (;;) - { - int t; - opcode = insn->match; - memset (&the_insn, '\0', sizeof (the_insn)); - fc = 0; - for (t = 0; t < MAX_FIXUPS; t++) - { - the_insn.fi[t].reloc = BFD_RELOC_NONE; - the_insn.fi[t].pcrel = 0; - the_insn.fi[t].fup = OP_NONE; - } - - /* Build the opcode, checking as we go that the operands match. */ - for (args = insn->args; ; ++args) - { - if (fc > MAX_FIXUPS) - abort (); - - switch (*args) - { - - /* End of args. */ - case '\0': - if (*s == '\0') - match = 1; - break; - - /* These must match exactly. */ - case '+': - case '(': - case ')': - case ',': - case ' ': - if (*s++ == *args) - continue; - break; - - /* Must be at least one digit. */ - case '#': - if (ISDIGIT (*s++)) - { - while (ISDIGIT (*s)) - ++s; - continue; - } - break; - - /* Next operand must be a register. */ - case '1': - case '2': - case 'd': - /* Check for register prefix if necessary. */ - if (reg_prefix && *s != reg_prefix) - goto error; - else if (reg_prefix) - s++; - - switch (*s) - { - /* Frame pointer. */ - case 'f': - s++; - if (*s++ == 'p') - { - mask = 0x3; - break; - } - goto error; - - /* Stack pointer. */ - case 's': - s++; - if (*s++ == 'p') - { - mask = 0x2; - break; - } - goto error; - - /* Any register r0..r31. */ - case 'r': - s++; - if (!ISDIGIT (c = *s++)) - { - goto error; - } - if (ISDIGIT (*s)) - { - if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) - goto error; - } - else - c -= '0'; - mask = c; - break; - - /* Not this opcode. */ - default: - goto error; - } - - /* Obtained the register, now place it in the opcode. */ - switch (*args) - { - case '1': - opcode |= mask << 11; - continue; - - case '2': - opcode |= mask << 21; - continue; - - case 'd': - opcode |= mask << 16; - continue; - - } - break; - - /* Next operand is a floating point register. */ - case 'e': - case 'f': - case 'g': - /* Check for register prefix if necessary. */ - if (reg_prefix && *s != reg_prefix) - goto error; - else if (reg_prefix) - s++; - - if (*s++ == 'f' && ISDIGIT (*s)) - { - mask = *s++; - if (ISDIGIT (*s)) - { - mask = 10 * (mask - '0') + (*s++ - '0'); - if (mask >= 32) - { - break; - } - } - else - mask -= '0'; - - switch (*args) - { - - case 'e': - opcode |= mask << 11; - continue; - - case 'f': - opcode |= mask << 21; - continue; - - case 'g': - opcode |= mask << 16; - if ((opcode & (1 << 10)) && mask != 0 - && (mask == ((opcode >> 11) & 0x1f))) - as_warn (_("Pipelined instruction: fsrc1 = fdest")); - continue; - } - } - break; - - /* Next operand must be a control register. */ - case 'c': - /* Check for register prefix if necessary. */ - if (reg_prefix && *s != reg_prefix) - goto error; - else if (reg_prefix) - s++; - - if (strncmp (s, "fir", 3) == 0) - { - opcode |= 0x0 << 21; - s += 3; - continue; - } - if (strncmp (s, "psr", 3) == 0) - { - opcode |= 0x1 << 21; - s += 3; - continue; - } - if (strncmp (s, "dirbase", 7) == 0) - { - opcode |= 0x2 << 21; - s += 7; - continue; - } - if (strncmp (s, "db", 2) == 0) - { - opcode |= 0x3 << 21; - s += 2; - continue; - } - if (strncmp (s, "fsr", 3) == 0) - { - opcode |= 0x4 << 21; - s += 3; - continue; - } - if (strncmp (s, "epsr", 4) == 0) - { - opcode |= 0x5 << 21; - s += 4; - continue; - } - /* The remaining control registers are XP only. */ - if (target_xp && strncmp (s, "bear", 4) == 0) - { - opcode |= 0x6 << 21; - s += 4; - continue; - } - if (target_xp && strncmp (s, "ccr", 3) == 0) - { - opcode |= 0x7 << 21; - s += 3; - continue; - } - if (target_xp && strncmp (s, "p0", 2) == 0) - { - opcode |= 0x8 << 21; - s += 2; - continue; - } - if (target_xp && strncmp (s, "p1", 2) == 0) - { - opcode |= 0x9 << 21; - s += 2; - continue; - } - if (target_xp && strncmp (s, "p2", 2) == 0) - { - opcode |= 0xa << 21; - s += 2; - continue; - } - if (target_xp && strncmp (s, "p3", 2) == 0) - { - opcode |= 0xb << 21; - s += 2; - continue; - } - break; - - /* 5-bit immediate in src1. */ - case '5': - if (! i860_get_expression (s)) - { - s = expr_end; - the_insn.fi[fc].fup |= OP_IMM_U5; - fc++; - continue; - } - break; - - /* 26-bit immediate, relative branch (lbroff). */ - case 'l': - the_insn.fi[fc].pcrel = 1; - the_insn.fi[fc].fup |= OP_IMM_BR26; - goto immediate; - - /* 16-bit split immediate, relative branch (sbroff). */ - case 'r': - the_insn.fi[fc].pcrel = 1; - the_insn.fi[fc].fup |= OP_IMM_BR16; - goto immediate; - - /* 16-bit split immediate. */ - case 's': - the_insn.fi[fc].fup |= OP_IMM_SPLIT16; - goto immediate; - - /* 16-bit split immediate, byte aligned (st.b). */ - case 'S': - the_insn.fi[fc].fup |= OP_IMM_SPLIT16; - goto immediate; - - /* 16-bit split immediate, half-word aligned (st.s). */ - case 'T': - the_insn.fi[fc].fup |= (OP_IMM_SPLIT16 | OP_ENCODE1 | OP_ALIGN2); - goto immediate; - - /* 16-bit split immediate, word aligned (st.l). */ - case 'U': - the_insn.fi[fc].fup |= (OP_IMM_SPLIT16 | OP_ENCODE1 | OP_ALIGN4); - goto immediate; - - /* 16-bit immediate. */ - case 'i': - the_insn.fi[fc].fup |= OP_IMM_S16; - goto immediate; - - /* 16-bit immediate, byte aligned (ld.b). */ - case 'I': - the_insn.fi[fc].fup |= OP_IMM_S16; - goto immediate; - - /* 16-bit immediate, half-word aligned (ld.s). */ - case 'J': - the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE1 | OP_ALIGN2); - goto immediate; - - /* 16-bit immediate, word aligned (ld.l, {p}fld.l, fst.l). */ - case 'K': - if (insn->name[0] == 'l') - the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE1 | OP_ALIGN4); - else - the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE2 | OP_ALIGN4); - goto immediate; - - /* 16-bit immediate, double-word aligned ({p}fld.d, fst.d). */ - case 'L': - the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE3 | OP_ALIGN8); - goto immediate; - - /* 16-bit immediate, quad-word aligned (fld.q, fst.q). */ - case 'M': - the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE3 | OP_ALIGN16); - - /*FALLTHROUGH*/ - - /* Handle the immediate for either the Intel syntax or - SVR4 syntax. The Intel syntax is "ha%immediate" - whereas SVR4 syntax is "[immediate]@ha". */ - immediate: - if (target_intel_syntax == 0) - { - /* AT&T/SVR4 syntax. */ - if (*s == ' ') - s++; - - /* Note that if i860_get_expression() fails, we will still - have created U entries in the symbol table for the - 'symbols' in the input string. Try not to create U - symbols for registers, etc. */ - if (! i860_get_expression (s)) - s = expr_end; - else - goto error; - - if (strncmp (s, "@ha", 3) == 0) - { - the_insn.fi[fc].fup |= OP_SEL_HA; - s += 3; - } - else if (strncmp (s, "@h", 2) == 0) - { - the_insn.fi[fc].fup |= OP_SEL_H; - s += 2; - } - else if (strncmp (s, "@l", 2) == 0) - { - the_insn.fi[fc].fup |= OP_SEL_L; - s += 2; - } - else if (strncmp (s, "@gotoff", 7) == 0 - || strncmp (s, "@GOTOFF", 7) == 0) - { - as_bad (_("Assembler does not yet support PIC")); - the_insn.fi[fc].fup |= OP_SEL_GOTOFF; - s += 7; - } - else if (strncmp (s, "@got", 4) == 0 - || strncmp (s, "@GOT", 4) == 0) - { - as_bad (_("Assembler does not yet support PIC")); - the_insn.fi[fc].fup |= OP_SEL_GOT; - s += 4; - } - else if (strncmp (s, "@plt", 4) == 0 - || strncmp (s, "@PLT", 4) == 0) - { - as_bad (_("Assembler does not yet support PIC")); - the_insn.fi[fc].fup |= OP_SEL_PLT; - s += 4; - } - - the_insn.expand = insn->expand; - fc++; - - continue; - } - else - { - /* Intel syntax. */ - if (*s == ' ') - s++; - if (strncmp (s, "ha%", 3) == 0) - { - the_insn.fi[fc].fup |= OP_SEL_HA; - s += 3; - } - else if (strncmp (s, "h%", 2) == 0) - { - the_insn.fi[fc].fup |= OP_SEL_H; - s += 2; - } - else if (strncmp (s, "l%", 2) == 0) - { - the_insn.fi[fc].fup |= OP_SEL_L; - s += 2; - } - the_insn.expand = insn->expand; - - /* Note that if i860_get_expression() fails, we will still - have created U entries in the symbol table for the - 'symbols' in the input string. Try not to create U - symbols for registers, etc. */ - if (! i860_get_expression (s)) - s = expr_end; - else - goto error; - - fc++; - continue; - } - break; - - default: - as_fatal (_("failed sanity check.")); - } - break; - } - error: - if (match == 0) - { - /* Args don't match. */ - if (insn[1].name != NULL - && ! strcmp (insn->name, insn[1].name)) - { - ++insn; - s = args_start; - continue; - } - else - { - as_bad (_("Illegal operands for %s"), insn->name); - return; - } - } - break; - } - - /* Set the dual bit on this instruction if necessary. */ - if (dual_mode != DUAL_OFF) - { - if ((opcode & 0xfc000000) == 0x48000000 || opcode == 0xb0000000) - { - /* The instruction is a flop or a fnop, so set its dual bit - (but check that it is 8-byte aligned). */ - if (((frag_now->fr_address + frag_now_fix_octets ()) & 7) == 0) - opcode |= (1 << 9); - else - as_bad (_("'d.%s' must be 8-byte aligned"), insn->name); - - if (dual_mode == DUAL_DDOT) - dual_mode = DUAL_OFF; - else if (dual_mode == DUAL_ONDDOT) - dual_mode = DUAL_ON; - } - else if (dual_mode == DUAL_DDOT || dual_mode == DUAL_ONDDOT) - as_bad (_("Prefix 'd.' invalid for instruction `%s'"), insn->name); - } - - the_insn.opcode = opcode; - - /* Only recognize XP instructions when the user has requested it. */ - if (insn->expand == XP_ONLY && ! target_xp) - as_bad (_("Unknown opcode: `%s'"), insn->name); -} - -static int -i860_get_expression (char *str) -{ - char *save_in; - segT seg; - - save_in = input_line_pointer; - input_line_pointer = str; - seg = expression (&the_insn.fi[fc].exp); - if (seg != absolute_section - && seg != undefined_section - && ! SEG_NORMAL (seg)) - { - the_insn.error = _("bad segment"); - expr_end = input_line_pointer; - input_line_pointer = save_in; - return 1; - } - expr_end = input_line_pointer; - input_line_pointer = save_in; - return 0; -} - -const char * -md_atof (int type, char *litP, int *sizeP) -{ - return ieee_md_atof (type, litP, sizeP, TRUE); -} - -/* Write out in current endian mode. */ -void -md_number_to_chars (char *buf, valueT val, int n) -{ - if (target_big_endian) - number_to_chars_bigendian (buf, val, n); - else - number_to_chars_littleendian (buf, val, n); -} - -/* This should never be called for i860. */ -int -md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED, - segT segtype ATTRIBUTE_UNUSED) -{ - as_fatal (_("relaxation not supported\n")); -} - -#ifdef DEBUG_I860 -static void -print_insn (struct i860_it *insn) -{ - if (insn->error) - fprintf (stderr, "ERROR: %s\n", insn->error); - - fprintf (stderr, "opcode = 0x%08lx\t", insn->opcode); - fprintf (stderr, "expand = 0x%x\t", insn->expand); - fprintf (stderr, "reloc = %s\t\n", - bfd_get_reloc_code_name (insn->reloc)); - fprintf (stderr, "exp = {\n"); - fprintf (stderr, "\t\tX_add_symbol = %s\n", - insn->exp.X_add_symbol ? - (S_GET_NAME (insn->exp.X_add_symbol) ? - S_GET_NAME (insn->exp.X_add_symbol) : "???") : "0"); - fprintf (stderr, "\t\tX_op_symbol = %s\n", - insn->exp.X_op_symbol ? - (S_GET_NAME (insn->exp.X_op_symbol) ? - S_GET_NAME (insn->exp.X_op_symbol) : "???") : "0"); - fprintf (stderr, "\t\tX_add_number = %lx\n", - insn->exp.X_add_number); - fprintf (stderr, "}\n"); -} -#endif /* DEBUG_I860 */ - - -#ifdef OBJ_ELF -const char *md_shortopts = "VQ:"; -#else -const char *md_shortopts = ""; -#endif - -#define OPTION_EB (OPTION_MD_BASE + 0) -#define OPTION_EL (OPTION_MD_BASE + 1) -#define OPTION_WARN_EXPAND (OPTION_MD_BASE + 2) -#define OPTION_XP (OPTION_MD_BASE + 3) -#define OPTION_INTEL_SYNTAX (OPTION_MD_BASE + 4) - -struct option md_longopts[] = { - { "EB", no_argument, NULL, OPTION_EB }, - { "EL", no_argument, NULL, OPTION_EL }, - { "mwarn-expand", no_argument, NULL, OPTION_WARN_EXPAND }, - { "mxp", no_argument, NULL, OPTION_XP }, - { "mintel-syntax",no_argument, NULL, OPTION_INTEL_SYNTAX }, - { NULL, no_argument, NULL, 0 } -}; -size_t md_longopts_size = sizeof (md_longopts); - -int -md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED) -{ - switch (c) - { - case OPTION_EB: - target_big_endian = 1; - break; - - case OPTION_EL: - target_big_endian = 0; - break; - - case OPTION_WARN_EXPAND: - target_warn_expand = 1; - break; - - case OPTION_XP: - target_xp = 1; - break; - - case OPTION_INTEL_SYNTAX: - target_intel_syntax = 1; - break; - -#ifdef OBJ_ELF - /* SVR4 argument compatibility (-V): print version ID. */ - case 'V': - print_version_id (); - break; - - /* SVR4 argument compatibility (-Qy, -Qn): controls whether - a .comment section should be emitted or not (ignored). */ - case 'Q': - break; -#endif - - default: - return 0; - } - - return 1; -} - -void -md_show_usage (FILE *stream) -{ - fprintf (stream, _("\ - -EL generate code for little endian mode (default)\n\ - -EB generate code for big endian mode\n\ - -mwarn-expand warn if pseudo operations are expanded\n\ - -mxp enable i860XP support (disabled by default)\n\ - -mintel-syntax enable Intel syntax (default to AT&T/SVR4)\n")); -#ifdef OBJ_ELF - /* SVR4 compatibility flags. */ - fprintf (stream, _("\ - -V print assembler version number\n\ - -Qy, -Qn ignored\n")); -#endif -} - - -/* We have no need to default values of symbols. */ -symbolS * -md_undefined_symbol (char *name ATTRIBUTE_UNUSED) -{ - return 0; -} - -/* The i860 denotes auto-increment with '++'. */ -void -md_operand (expressionS *exp) -{ - char *s; - - for (s = input_line_pointer; *s; s++) - { - if (s[0] == '+' && s[1] == '+') - { - input_line_pointer += 2; - exp->X_op = O_register; - break; - } - } -} - -/* Round up a section size to the appropriate boundary. */ -valueT -md_section_align (segT segment ATTRIBUTE_UNUSED, - valueT size ATTRIBUTE_UNUSED) -{ - /* Byte alignment is fine. */ - return size; -} - -/* On the i860, a PC-relative offset is relative to the address of the - offset plus its size. */ -long -md_pcrel_from (fixS *fixP) -{ - return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; -} - -/* Determine the relocation needed for non PC-relative 16-bit immediates. - Also adjust the given immediate as necessary. Finally, check that - all constraints (such as alignment) are satisfied. */ -static bfd_reloc_code_real_type -obtain_reloc_for_imm16 (fixS *fix, long *val) -{ - valueT fup = fix->fx_addnumber; - bfd_reloc_code_real_type reloc; - - if (fix->fx_pcrel) - abort (); - - /* Check alignment restrictions. */ - if ((fup & OP_ALIGN2) && (*val & 0x1)) - as_bad_where (fix->fx_file, fix->fx_line, - _("This immediate requires 0 MOD 2 alignment")); - else if ((fup & OP_ALIGN4) && (*val & 0x3)) - as_bad_where (fix->fx_file, fix->fx_line, - _("This immediate requires 0 MOD 4 alignment")); - else if ((fup & OP_ALIGN8) && (*val & 0x7)) - as_bad_where (fix->fx_file, fix->fx_line, - _("This immediate requires 0 MOD 8 alignment")); - else if ((fup & OP_ALIGN16) && (*val & 0xf)) - as_bad_where (fix->fx_file, fix->fx_line, - _("This immediate requires 0 MOD 16 alignment")); - - if (fup & OP_SEL_HA) - { - *val = (*val >> 16) + (*val & 0x8000 ? 1 : 0); - reloc = BFD_RELOC_860_HIGHADJ; - } - else if (fup & OP_SEL_H) - { - *val >>= 16; - reloc = BFD_RELOC_860_HIGH; - } - else if (fup & OP_SEL_L) - { - int num_encode; - if (fup & OP_IMM_SPLIT16) - { - if (fup & OP_ENCODE1) - { - num_encode = 1; - reloc = BFD_RELOC_860_SPLIT1; - } - else if (fup & OP_ENCODE2) - { - num_encode = 2; - reloc = BFD_RELOC_860_SPLIT2; - } - else - { - num_encode = 0; - reloc = BFD_RELOC_860_SPLIT0; - } - } - else - { - if (fup & OP_ENCODE1) - { - num_encode = 1; - reloc = BFD_RELOC_860_LOW1; - } - else if (fup & OP_ENCODE2) - { - num_encode = 2; - reloc = BFD_RELOC_860_LOW2; - } - else if (fup & OP_ENCODE3) - { - num_encode = 3; - reloc = BFD_RELOC_860_LOW3; - } - else - { - num_encode = 0; - reloc = BFD_RELOC_860_LOW0; - } - } - - /* Preserve size encode bits. */ - *val &= ~((1 << num_encode) - 1); - } - else - { - /* No selector. What reloc do we generate (???)? */ - reloc = BFD_RELOC_32; - } - - return reloc; -} - -/* Attempt to simplify or eliminate a fixup. To indicate that a fixup - has been eliminated, set fix->fx_done. If fix->fx_addsy is non-NULL, - we will have to generate a reloc entry. */ - -void -md_apply_fix (fixS *fix, valueT *valP, segT seg ATTRIBUTE_UNUSED) -{ - char *buf; - long val = *valP; - unsigned long insn; - valueT fup; - - buf = fix->fx_frag->fr_literal + fix->fx_where; - - /* Recall that earlier we stored the opcode little-endian. */ - insn = bfd_getl32 (buf); - - /* We stored a fix-up in this oddly-named scratch field. */ - fup = fix->fx_addnumber; - - /* Determine the necessary relocations as well as inserting an - immediate into the instruction. */ - if (fup & OP_IMM_U5) - { - if (val & ~0x1f) - as_bad_where (fix->fx_file, fix->fx_line, - _("5-bit immediate too large")); - if (fix->fx_addsy) - as_bad_where (fix->fx_file, fix->fx_line, - _("5-bit field must be absolute")); - - insn |= (val & 0x1f) << 11; - bfd_putl32 (insn, buf); - fix->fx_r_type = BFD_RELOC_NONE; - fix->fx_done = 1; - } - else if (fup & OP_IMM_S16) - { - fix->fx_r_type = obtain_reloc_for_imm16 (fix, &val); - - /* Insert the immediate. */ - if (fix->fx_addsy) - fix->fx_done = 0; - else - { - insn |= val & 0xffff; - bfd_putl32 (insn, buf); - fix->fx_r_type = BFD_RELOC_NONE; - fix->fx_done = 1; - } - } - else if (fup & OP_IMM_U16) - abort (); - - else if (fup & OP_IMM_SPLIT16) - { - fix->fx_r_type = obtain_reloc_for_imm16 (fix, &val); - - /* Insert the immediate. */ - if (fix->fx_addsy) - fix->fx_done = 0; - else - { - insn |= val & 0x7ff; - insn |= (val & 0xf800) << 5; - bfd_putl32 (insn, buf); - fix->fx_r_type = BFD_RELOC_NONE; - fix->fx_done = 1; - } - } - else if (fup & OP_IMM_BR16) - { - if (val & 0x3) - as_bad_where (fix->fx_file, fix->fx_line, - _("A branch offset requires 0 MOD 4 alignment")); - - val = val >> 2; - - /* Insert the immediate. */ - if (fix->fx_addsy) - { - fix->fx_done = 0; - fix->fx_r_type = BFD_RELOC_860_PC16; - } - else - { - insn |= (val & 0x7ff); - insn |= ((val & 0xf800) << 5); - bfd_putl32 (insn, buf); - fix->fx_r_type = BFD_RELOC_NONE; - fix->fx_done = 1; - } - } - else if (fup & OP_IMM_BR26) - { - if (val & 0x3) - as_bad_where (fix->fx_file, fix->fx_line, - _("A branch offset requires 0 MOD 4 alignment")); - - val >>= 2; - - /* Insert the immediate. */ - if (fix->fx_addsy) - { - fix->fx_r_type = BFD_RELOC_860_PC26; - fix->fx_done = 0; - } - else - { - insn |= (val & 0x3ffffff); - bfd_putl32 (insn, buf); - fix->fx_r_type = BFD_RELOC_NONE; - fix->fx_done = 1; - } - } - else if (fup != OP_NONE) - { - as_bad_where (fix->fx_file, fix->fx_line, - _("Unrecognized fix-up (0x%08lx)"), (unsigned long) fup); - abort (); - } - else - { - /* I believe only fix-ups such as ".long .ep.main-main+0xc8000000" - reach here (???). */ - if (fix->fx_addsy) - { - fix->fx_r_type = BFD_RELOC_32; - fix->fx_done = 0; - } - else - { - insn |= (val & 0xffffffff); - bfd_putl32 (insn, buf); - fix->fx_r_type = BFD_RELOC_NONE; - fix->fx_done = 1; - } - } -} - -/* Generate a machine dependent reloc from a fixup. */ -arelent* -tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, - fixS *fixp) -{ - arelent *reloc; - - reloc = XNEW (arelent); - reloc->sym_ptr_ptr = XNEW (asymbol *); - *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); - reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; - reloc->addend = fixp->fx_offset; - reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); - - if (! reloc->howto) - { - as_bad_where (fixp->fx_file, fixp->fx_line, - "Cannot represent %s relocation in object file", - bfd_get_reloc_code_name (fixp->fx_r_type)); - } - return reloc; -} - -/* This is called from HANDLE_ALIGN in write.c. Fill in the contents - of an rs_align_code fragment. */ - -void -i860_handle_align (fragS *fragp) -{ - /* Instructions are always stored little-endian on the i860. */ - static const unsigned char le_nop[] = { 0x00, 0x00, 0x00, 0xA0 }; - - int bytes; - char *p; - - if (fragp->fr_type != rs_align_code) - return; - - bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; - p = fragp->fr_literal + fragp->fr_fix; - - /* Make sure we are on a 4-byte boundary, in case someone has been - putting data into a text section. */ - if (bytes & 3) - { - int fix = bytes & 3; - memset (p, 0, fix); - p += fix; - fragp->fr_fix += fix; - } - - memcpy (p, le_nop, 4); - fragp->fr_var = 4; -} - -/* This is called after a user-defined label is seen. We check - if the label has a double colon (valid in Intel syntax mode only), - in which case it should be externalized. */ - -void -i860_check_label (symbolS *labelsym) -{ - /* At this point, the current line pointer is sitting on the character - just after the first colon on the label. */ - if (target_intel_syntax && *input_line_pointer == ':') - { - S_SET_EXTERNAL (labelsym); - input_line_pointer++; - } -} diff --git a/gas/config/tc-i860.h b/gas/config/tc-i860.h deleted file mode 100644 index a63f82f..0000000 --- a/gas/config/tc-i860.h +++ /dev/null @@ -1,95 +0,0 @@ -/* tc-i860.h -- Header file for the i860. - Copyright (C) 1991-2018 Free Software Foundation, Inc. - - Brought back from the dead and completely reworked - by Jason Eckhardt . - - This file is part of GAS, the GNU Assembler. - - GAS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GAS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License along - with GAS; see the file COPYING. If not, write to the Free Software - Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef TC_I860 -#define TC_I860 1 - -enum i860_fix_info -{ - OP_NONE = 0x00000, - OP_IMM_U5 = 0x00001, - OP_IMM_S16 = 0x00002, - OP_IMM_U16 = 0x00004, - OP_IMM_SPLIT16 = 0x00008, - OP_IMM_BR26 = 0x00010, - OP_IMM_BR16 = 0x00020, - OP_ENCODE1 = 0x00040, - OP_ENCODE2 = 0x00080, - OP_ENCODE3 = 0x00100, - OP_SEL_HA = 0x00200, - OP_SEL_H = 0x00400, - OP_SEL_L = 0x00800, - OP_SEL_GOT = 0x01000, - OP_SEL_GOTOFF = 0x02000, - OP_SEL_PLT = 0x04000, - OP_ALIGN2 = 0x08000, - OP_ALIGN4 = 0x10000, - OP_ALIGN8 = 0x20000, - OP_ALIGN16 = 0x40000 -}; - -/* Set the endianness we are using. Default to little endian. */ -#ifndef TARGET_BYTES_BIG_ENDIAN -#define TARGET_BYTES_BIG_ENDIAN 0 -#endif - -/* Whether or not the target is big endian. */ -extern int target_big_endian; - -/* BFD target architecture. */ -#define TARGET_ARCH bfd_arch_i860 - -/* The target BFD format. */ -#ifdef OBJ_ELF -#define TARGET_FORMAT (target_big_endian ? "elf32-i860" : "elf32-i860-little") -#else -#error i860 GAS currently supports only the ELF object format -#endif - -#define WORKING_DOT_WORD -#define DIFF_EXPR_OK - -/* Permit temporary numeric labels. */ -#define LOCAL_LABELS_FB 1 -#define LISTING_HEADER "GAS for i860" - -#define md_convert_frag(b,s,f) abort () - -/* Values passed to md_apply_fix don't include the symbol value. */ -#define MD_APPLY_SYM_VALUE(FIX) 0 - -/* No shared lib support, so we don't need to ensure externally - visible symbols can be overridden. */ -#define EXTERN_FORCE_RELOC 0 - -/* Bits for post-processing of a user defined label to check if - it has a double colon (Intel syntax only). */ -extern void i860_check_label (symbolS *labelsym); -#define tc_check_label(ls) i860_check_label (ls) - -/* Bits for filling in rs_align_code fragments with NOPs. */ -extern void i860_handle_align (struct frag *); -#define HANDLE_ALIGN(fragp) i860_handle_align (fragp) - -#define MAX_MEM_FOR_RS_ALIGN_CODE (3 + 4 + 4) - -#endif /* TC_I860 */ diff --git a/gas/config/tc-i960.c b/gas/config/tc-i960.c deleted file mode 100644 index e6f7504..0000000 --- a/gas/config/tc-i960.c +++ /dev/null @@ -1,2667 +0,0 @@ -/* tc-i960.c - All the i80960-specific stuff - Copyright (C) 1989-2018 Free Software Foundation, Inc. - - This file is part of GAS. - - GAS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GAS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS; see the file COPYING. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -/* See comment on md_parse_option for 80960-specific invocation options. */ - -/* There are 4 different lengths of (potentially) symbol-based displacements - in the 80960 instruction set, each of which could require address fix-ups - and (in the case of external symbols) emission of relocation directives: - - 32-bit (MEMB) - This is a standard length for the base assembler and requires no - special action. - - 13-bit (COBR) - This is a non-standard length, but the base assembler has a - hook for bit field address fixups: the fixS structure can - point to a descriptor of the field, in which case our - md_number_to_field() routine gets called to process it. - - I made the hook a little cleaner by having fix_new() (in the base - assembler) return a pointer to the fixS in question. And I made it a - little simpler by storing the field size (in this case 13) instead of - of a pointer to another structure: 80960 displacements are ALWAYS - stored in the low-order bits of a 4-byte word. - - Since the target of a COBR cannot be external, no relocation - directives for this size displacement have to be generated. - But the base assembler had to be modified to issue error - messages if the symbol did turn out to be external. - - 24-bit (CTRL) - Fixups are handled as for the 13-bit case (except that 24 is stored - in the fixS). - - The relocation directive generated is the same as that for the 32-bit - displacement, except that it's PC-relative (the 32-bit displacement - never is). The i80960 version of the linker needs a mod to - distinguish and handle the 24-bit case. - - 12-bit (MEMA) - MEMA formats are always promoted to MEMB (32-bit) if the displacement - is based on a symbol, because it could be relocated at link time. - The only time we use the 12-bit format is if an absolute value of - less than 4096 is specified, in which case we need neither a fixup nor - a relocation directive. */ - -#include "as.h" - -#include "safe-ctype.h" - -#include "opcode/i960.h" - -#if defined (OBJ_AOUT) || defined (OBJ_BOUT) - -#define TC_S_IS_SYSPROC(s) ((1 <= S_GET_OTHER (s)) && (S_GET_OTHER (s) <= 32)) -#define TC_S_IS_BALNAME(s) (S_GET_OTHER (s) == N_BALNAME) -#define TC_S_IS_CALLNAME(s) (S_GET_OTHER (s) == N_CALLNAME) -#define TC_S_IS_BADPROC(s) ((S_GET_OTHER (s) != 0) && !TC_S_IS_CALLNAME (s) && !TC_S_IS_BALNAME (s) && !TC_S_IS_SYSPROC (s)) - -#define TC_S_SET_SYSPROC(s, p) (S_SET_OTHER ((s), (p) + 1)) -#define TC_S_GET_SYSPROC(s) (S_GET_OTHER (s) - 1) - -#define TC_S_FORCE_TO_BALNAME(s) (S_SET_OTHER ((s), N_BALNAME)) -#define TC_S_FORCE_TO_CALLNAME(s) (S_SET_OTHER ((s), N_CALLNAME)) -#define TC_S_FORCE_TO_SYSPROC(s) {;} - -#else /* ! OBJ_A/BOUT */ -#ifdef OBJ_COFF - -#define TC_S_IS_SYSPROC(s) (S_GET_STORAGE_CLASS (s) == C_SCALL) -#define TC_S_IS_BALNAME(s) (SF_GET_BALNAME (s)) -#define TC_S_IS_CALLNAME(s) (SF_GET_CALLNAME (s)) -#define TC_S_IS_BADPROC(s) (TC_S_IS_SYSPROC (s) && TC_S_GET_SYSPROC (s) < 0 && 31 < TC_S_GET_SYSPROC (s)) - -#define TC_S_SET_SYSPROC(s, p) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p)) -#define TC_S_GET_SYSPROC(s) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx) - -#define TC_S_FORCE_TO_BALNAME(s) (SF_SET_BALNAME (s)) -#define TC_S_FORCE_TO_CALLNAME(s) (SF_SET_CALLNAME (s)) -#define TC_S_FORCE_TO_SYSPROC(s) (S_SET_STORAGE_CLASS ((s), C_SCALL)) - -#else /* ! OBJ_COFF */ -#ifdef OBJ_ELF -#define TC_S_IS_SYSPROC(s) 0 - -#define TC_S_IS_BALNAME(s) 0 -#define TC_S_IS_CALLNAME(s) 0 -#define TC_S_IS_BADPROC(s) 0 - -#define TC_S_SET_SYSPROC(s, p) -#define TC_S_GET_SYSPROC(s) 0 - -#define TC_S_FORCE_TO_BALNAME(s) -#define TC_S_FORCE_TO_CALLNAME(s) -#define TC_S_FORCE_TO_SYSPROC(s) -#else - #error COFF, a.out, b.out, and ELF are the only supported formats. -#endif /* ! OBJ_ELF */ -#endif /* ! OBJ_COFF */ -#endif /* ! OBJ_A/BOUT */ - -extern char *input_line_pointer; - -/* Local i80960 routines. */ -struct memS; -struct regop; - -/* See md_parse_option() for meanings of these options. */ -static char norelax; /* True if -norelax switch seen. */ -static char instrument_branches; /* True if -b switch seen. */ - -/* Characters that always start a comment. - If the pre-processor is disabled, these aren't very useful. */ -const char comment_chars[] = "#"; - -/* Characters that only start a comment at the beginning of - a line. If the line seems to have the form '# 123 filename' - .line and .file directives will appear in the pre-processed output. - - Note that input_file.c hand checks for '#' at the beginning of the - first line of the input file. This is because the compiler outputs - #NO_APP at the beginning of its output. */ - -/* Also note that comments started like this one will always work. */ - -const char line_comment_chars[] = "#"; -const char line_separator_chars[] = ";"; - -/* Chars that can be used to separate mant from exp in floating point nums. */ -const char EXP_CHARS[] = "eE"; - -/* Chars that mean this number is a floating point constant, - as in 0f12.456 or 0d1.2345e12. */ -const char FLT_CHARS[] = "fFdDtT"; - -/* Table used by base assembler to relax addresses based on varying length - instructions. The fields are: - 1) most positive reach of this state, - 2) most negative reach of this state, - 3) how many bytes this mode will add to the size of the current frag - 4) which index into the table to try if we can't fit into this one. - - For i80960, the only application is the (de-)optimization of cobr - instructions into separate compare and branch instructions when a 13-bit - displacement won't hack it. */ -const relax_typeS md_relax_table[] = -{ - {0, 0, 0, 0}, /* State 0 => no more relaxation possible. */ - {4088, -4096, 0, 2}, /* State 1: conditional branch (cobr). */ - {0x800000 - 8, -0x800000, 4, 0}, /* State 2: compare (reg) & branch (ctrl). */ -}; - -/* These are the machine dependent pseudo-ops. - - This table describes all the machine specific pseudo-ops the assembler - has to support. The fields are: - pseudo-op name without dot - function to call to execute this pseudo-op - integer arg to pass to the function. */ -#define S_LEAFPROC 1 -#define S_SYSPROC 2 - -/* Macros to extract info from an 'expressionS' structure 'e'. */ -#define adds(e) e.X_add_symbol -#define offs(e) e.X_add_number - -/* Branch-prediction bits for CTRL/COBR format opcodes. */ -#define BP_MASK 0x00000002 /* Mask for branch-prediction bit. */ -#define BP_TAKEN 0x00000000 /* Value to OR in to predict branch. */ -#define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch. */ - -/* Some instruction opcodes that we need explicitly. */ -#define BE 0x12000000 -#define BG 0x11000000 -#define BGE 0x13000000 -#define BL 0x14000000 -#define BLE 0x16000000 -#define BNE 0x15000000 -#define BNO 0x10000000 -#define BO 0x17000000 -#define CHKBIT 0x5a002700 -#define CMPI 0x5a002080 -#define CMPO 0x5a002000 - -#define B 0x08000000 -#define BAL 0x0b000000 -#define CALL 0x09000000 -#define CALLS 0x66003800 -#define RET 0x0a000000 - -/* These masks are used to build up a set of MEMB mode bits. */ -#define A_BIT 0x0400 -#define I_BIT 0x0800 -#define MEMB_BIT 0x1000 -#define D_BIT 0x2000 - -/* Mask for the only mode bit in a MEMA instruction (if set, abase reg is - used). */ -#define MEMA_ABASE 0x2000 - -/* Info from which a MEMA or MEMB format instruction can be generated. */ -typedef struct memS - { - /* (First) 32 bits of instruction. */ - long opcode; - /* 0-(none), 12- or, 32-bit displacement needed. */ - int disp; - /* The expression in the source instruction from which the - displacement should be determined. */ - char *e; - } -memS; - -/* The two pieces of info we need to generate a register operand. */ -struct regop - { - int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg. */ - int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0). */ - int n; /* Register number or literal value. */ - }; - -/* Number and assembler mnemonic for all registers that can appear in - operands. */ -static const struct - { - const char *reg_name; - int reg_num; - } -regnames[] = -{ - { "pfp", 0 }, - { "sp", 1 }, - { "rip", 2 }, - { "r3", 3 }, - { "r4", 4 }, - { "r5", 5 }, - { "r6", 6 }, - { "r7", 7 }, - { "r8", 8 }, - { "r9", 9 }, - { "r10", 10 }, - { "r11", 11 }, - { "r12", 12 }, - { "r13", 13 }, - { "r14", 14 }, - { "r15", 15 }, - { "g0", 16 }, - { "g1", 17 }, - { "g2", 18 }, - { "g3", 19 }, - { "g4", 20 }, - { "g5", 21 }, - { "g6", 22 }, - { "g7", 23 }, - { "g8", 24 }, - { "g9", 25 }, - { "g10", 26 }, - { "g11", 27 }, - { "g12", 28 }, - { "g13", 29 }, - { "g14", 30 }, - { "fp", 31 }, - - /* Numbers for special-function registers are for assembler internal - use only: they are scaled back to range [0-31] for binary output. */ -#define SF0 32 - - { "sf0", 32 }, - { "sf1", 33 }, - { "sf2", 34 }, - { "sf3", 35 }, - { "sf4", 36 }, - { "sf5", 37 }, - { "sf6", 38 }, - { "sf7", 39 }, - { "sf8", 40 }, - { "sf9", 41 }, - { "sf10", 42 }, - { "sf11", 43 }, - { "sf12", 44 }, - { "sf13", 45 }, - { "sf14", 46 }, - { "sf15", 47 }, - { "sf16", 48 }, - { "sf17", 49 }, - { "sf18", 50 }, - { "sf19", 51 }, - { "sf20", 52 }, - { "sf21", 53 }, - { "sf22", 54 }, - { "sf23", 55 }, - { "sf24", 56 }, - { "sf25", 57 }, - { "sf26", 58 }, - { "sf27", 59 }, - { "sf28", 60 }, - { "sf29", 61 }, - { "sf30", 62 }, - { "sf31", 63 }, - - /* Numbers for floating point registers are for assembler internal - use only: they are scaled back to [0-3] for binary output. */ -#define FP0 64 - - { "fp0", 64 }, - { "fp1", 65 }, - { "fp2", 66 }, - { "fp3", 67 }, - - { NULL, 0 }, /* END OF LIST */ -}; - -#define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0)) -#define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0)) -#define IS_FP_REG(n) ((n) >= FP0) - -/* Number and assembler mnemonic for all registers that can appear as - 'abase' (indirect addressing) registers. */ -static const struct -{ - const char *areg_name; - int areg_num; -} -aregs[] = -{ - { "(pfp)", 0 }, - { "(sp)", 1 }, - { "(rip)", 2 }, - { "(r3)", 3 }, - { "(r4)", 4 }, - { "(r5)", 5 }, - { "(r6)", 6 }, - { "(r7)", 7 }, - { "(r8)", 8 }, - { "(r9)", 9 }, - { "(r10)", 10 }, - { "(r11)", 11 }, - { "(r12)", 12 }, - { "(r13)", 13 }, - { "(r14)", 14 }, - { "(r15)", 15 }, - { "(g0)", 16 }, - { "(g1)", 17 }, - { "(g2)", 18 }, - { "(g3)", 19 }, - { "(g4)", 20 }, - { "(g5)", 21 }, - { "(g6)", 22 }, - { "(g7)", 23 }, - { "(g8)", 24 }, - { "(g9)", 25 }, - { "(g10)", 26 }, - { "(g11)", 27 }, - { "(g12)", 28 }, - { "(g13)", 29 }, - { "(g14)", 30 }, - { "(fp)", 31 }, - -#define IPREL 32 - /* For assembler internal use only: this number never appears in binary - output. */ - { "(ip)", IPREL }, - - { NULL, 0 }, /* END OF LIST */ -}; - -/* Hash tables. */ -static struct hash_control *op_hash; /* Opcode mnemonics. */ -static struct hash_control *reg_hash; /* Register name hash table. */ -static struct hash_control *areg_hash; /* Abase register hash table. */ - -/* Architecture for which we are assembling. */ -#define ARCH_ANY 0 /* Default: no architecture checking done. */ -#define ARCH_KA 1 -#define ARCH_KB 2 -#define ARCH_MC 3 -#define ARCH_CA 4 -#define ARCH_JX 5 -#define ARCH_HX 6 -int architecture = ARCH_ANY; /* Architecture requested on invocation line. */ -int iclasses_seen; /* OR of instruction classes (I_* constants) - for which we've actually assembled - instructions. */ - -/* BRANCH-PREDICTION INSTRUMENTATION - - The following supports generation of branch-prediction instrumentation - (turned on by -b switch). The instrumentation collects counts - of branches taken/not-taken for later input to a utility that will - set the branch prediction bits of the instructions in accordance with - the behavior observed. (Note that the KX series does not have - branch-prediction.) - - The instrumentation consists of: - - (1) before and after each conditional branch, a call to an external - routine that increments and steps over an inline counter. The - counter itself, initialized to 0, immediately follows the call - instruction. For each branch, the counter following the branch - is the number of times the branch was not taken, and the difference - between the counters is the number of times it was taken. An - example of an instrumented conditional branch: - - call BR_CNT_FUNC - .word 0 - LBRANCH23: be label - call BR_CNT_FUNC - .word 0 - - (2) a table of pointers to the instrumented branches, so that an - external postprocessing routine can locate all of the counters. - the table begins with a 2-word header: a pointer to the next in - a linked list of such tables (initialized to 0); and a count - of the number of entries in the table (exclusive of the header. - - Note that input source code is expected to already contain calls - an external routine that will link the branch local table into a - list of such tables. */ - -/* Number of branches instrumented so far. Also used to generate - unique local labels for each instrumented branch. */ -static int br_cnt; - -#define BR_LABEL_BASE "LBRANCH" -/* Basename of local labels on instrumented branches, to avoid - conflict with compiler- generated local labels. */ - -#define BR_CNT_FUNC "__inc_branch" -/* Name of the external routine that will increment (and step over) an - inline counter. */ - -#define BR_TAB_NAME "__BRANCH_TABLE__" -/* Name of the table of pointers to branches. A local (i.e., - non-external) symbol. */ - -static void ctrl_fmt (const char *, long, int); - - -void -md_begin (void) -{ - int i; /* Loop counter. */ - const struct i960_opcode *oP; /* Pointer into opcode table. */ - const char *retval; /* Value returned by hash functions. */ - - op_hash = hash_new (); - reg_hash = hash_new (); - areg_hash = hash_new (); - - /* For some reason, the base assembler uses an empty string for "no - error message", instead of a NULL pointer. */ - retval = 0; - - for (oP = i960_opcodes; oP->name && !retval; oP++) - retval = hash_insert (op_hash, oP->name, (void *) oP); - - for (i = 0; regnames[i].reg_name && !retval; i++) - retval = hash_insert (reg_hash, regnames[i].reg_name, - (char *) ®names[i].reg_num); - - for (i = 0; aregs[i].areg_name && !retval; i++) - retval = hash_insert (areg_hash, aregs[i].areg_name, - (char *) &aregs[i].areg_num); - - if (retval) - as_fatal (_("Hashing returned \"%s\"."), retval); -} - -/* parse_expr: parse an expression - - Use base assembler's expression parser to parse an expression. - It, unfortunately, runs off a global which we have to save/restore - in order to make it work for us. - - An empty expression string is treated as an absolute 0. - - Sets O_illegal regardless of expression evaluation if entire input - string is not consumed in the evaluation -- tolerate no dangling junk! */ - -static void -parse_expr (const char *textP, /* Text of expression to be parsed. */ - expressionS *expP) /* Where to put the results of parsing. */ -{ - char *save_in; /* Save global here. */ - symbolS *symP; - - know (textP); - - if (*textP == '\0') - { - /* Treat empty string as absolute 0. */ - expP->X_add_symbol = expP->X_op_symbol = NULL; - expP->X_add_number = 0; - expP->X_op = O_constant; - } - else - { - save_in = input_line_pointer; /* Save global. */ - input_line_pointer = (char *) textP; /* Make parser work for us. */ - - (void) expression (expP); - if ((size_t) (input_line_pointer - textP) != strlen (textP)) - /* Did not consume all of the input. */ - expP->X_op = O_illegal; - - symP = expP->X_add_symbol; - if (symP && (hash_find (reg_hash, S_GET_NAME (symP)))) - /* Register name in an expression. */ - /* FIXME: this isn't much of a check any more. */ - expP->X_op = O_illegal; - - input_line_pointer = save_in; /* Restore global. */ - } -} - -/* emit: output instruction binary - - Output instruction binary, in target byte order, 4 bytes at a time. - Return pointer to where it was placed. */ - -static char * -emit (long instr) /* Word to be output, host byte order. */ -{ - char *toP; /* Where to output it. */ - - toP = frag_more (4); /* Allocate storage. */ - md_number_to_chars (toP, instr, 4); /* Convert to target byte order. */ - return toP; -} - -/* get_cdisp: handle displacement for a COBR or CTRL instruction. - - Parse displacement for a COBR or CTRL instruction. - - If successful, output the instruction opcode and set up for it, - depending on the arg 'var_frag', either: - o an address fixup to be done when all symbol values are known, or - o a varying length code fragment, with address fixup info. This - will be done for cobr instructions that may have to be relaxed - in to compare/branch instructions (8 bytes) if the final - address displacement is greater than 13 bits. */ - -static void -get_cdisp (const char *dispP, /* Displacement as specified in source instruction. */ - const char *ifmtP, /* "COBR" or "CTRL" (for use in error message). */ - long instr, /* Instruction needing the displacement. */ - int numbits, /* # bits of displacement (13 for COBR, 24 for CTRL). */ - int var_frag,/* 1 if varying length code fragment should be emitted; - 0 if an address fix should be emitted. */ - int callj) /* 1 if callj relocation should be done; else 0. */ -{ - expressionS e; /* Parsed expression. */ - fixS *fixP; /* Structure describing needed address fix. */ - char *outP; /* Where instruction binary is output to. */ - - fixP = NULL; - - parse_expr (dispP, &e); - switch (e.X_op) - { - case O_illegal: - as_bad (_("expression syntax error")); - break; - - case O_symbol: - if (S_GET_SEGMENT (e.X_add_symbol) == now_seg - || S_GET_SEGMENT (e.X_add_symbol) == undefined_section) - { - if (var_frag) - { - outP = frag_more (8); /* Allocate worst-case storage. */ - md_number_to_chars (outP, instr, 4); - frag_variant (rs_machine_dependent, 4, 4, 1, - adds (e), offs (e), outP); - } - else - { - /* Set up a new fix structure, so address can be updated - when all symbol values are known. */ - outP = emit (instr); - fixP = fix_new (frag_now, - outP - frag_now->fr_literal, - 4, - adds (e), - offs (e), - 1, - NO_RELOC); - - fixP->fx_tcbit = callj; - - /* We want to modify a bit field when the address is - known. But we don't need all the garbage in the - bit_fix structure. So we're going to lie and store - the number of bits affected instead of a pointer. */ - fixP->fx_bit_fixP = (bit_fixS *) (size_t) numbits; - } - } - else - as_bad (_("attempt to branch into different segment")); - break; - - default: - as_bad (_("target of %s instruction must be a label"), ifmtP); - break; - } -} - -static int -md_chars_to_number (char * val, /* Value in target byte order. */ - int n) /* Number of bytes in the input. */ -{ - int retval; - - for (retval = 0; n--;) - { - retval <<= 8; - retval |= (unsigned char) val[n]; - } - return retval; -} - -/* mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode. - - There are 2 possible MEMA formats: - - displacement only - - displacement + abase - - They are distinguished by the setting of the MEMA_ABASE bit. */ - -static void -mema_to_memb (char * opcodeP) /* Where to find the opcode, in target byte order. */ -{ - long opcode; /* Opcode in host byte order. */ - long mode; /* Mode bits for MEMB instruction. */ - - opcode = md_chars_to_number (opcodeP, 4); - know (!(opcode & MEMB_BIT)); - - mode = MEMB_BIT | D_BIT; - if (opcode & MEMA_ABASE) - mode |= A_BIT; - - opcode &= 0xffffc000; /* Clear MEMA offset and mode bits. */ - opcode |= mode; /* Set MEMB mode bits. */ - - md_number_to_chars (opcodeP, opcode, 4); -} - -/* targ_has_sfr: - - Return TRUE iff the target architecture supports the specified - special-function register (sfr). */ - -static int -targ_has_sfr (int n) /* Number (0-31) of sfr. */ -{ - switch (architecture) - { - case ARCH_KA: - case ARCH_KB: - case ARCH_MC: - case ARCH_JX: - return 0; - case ARCH_HX: - return ((0 <= n) && (n <= 4)); - case ARCH_CA: - default: - return ((0 <= n) && (n <= 2)); - } -} - -/* Look up a (suspected) register name in the register table and return the - associated register number (or -1 if not found). */ - -static int -get_regnum (char *regname) /* Suspected register name. */ -{ - int *rP; - - rP = (int *) hash_find (reg_hash, regname); - return (rP == NULL) ? -1 : *rP; -} - -/* syntax: Issue a syntax error. */ - -static void -syntax (void) -{ - as_bad (_("syntax error")); -} - -/* parse_regop: parse a register operand. - - In case of illegal operand, issue a message and return some valid - information so instruction processing can continue. */ - -static void -parse_regop (struct regop *regopP, /* Where to put description of register operand. */ - char *optext, /* Text of operand. */ - char opdesc) /* Descriptor byte: what's legal for this operand. */ -{ - int n; /* Register number. */ - expressionS e; /* Parsed expression. */ - - /* See if operand is a register. */ - n = get_regnum (optext); - if (n >= 0) - { - if (IS_RG_REG (n)) - { - /* Global or local register. */ - if (!REG_ALIGN (opdesc, n)) - as_bad (_("unaligned register")); - - regopP->n = n; - regopP->mode = 0; - regopP->special = 0; - return; - } - else if (IS_FP_REG (n) && FP_OK (opdesc)) - { - /* Floating point register, and it's allowed. */ - regopP->n = n - FP0; - regopP->mode = 1; - regopP->special = 0; - return; - } - else if (IS_SF_REG (n) && SFR_OK (opdesc)) - { - /* Special-function register, and it's allowed. */ - regopP->n = n - SF0; - regopP->mode = 0; - regopP->special = 1; - if (!targ_has_sfr (regopP->n)) - as_bad (_("no such sfr in this architecture")); - - return; - } - } - else if (LIT_OK (opdesc)) - { - /* How about a literal? */ - regopP->mode = 1; - regopP->special = 0; - if (FP_OK (opdesc)) - { - /* Floating point literal acceptable. */ - /* Skip over 0f, 0d, or 0e prefix. */ - if ((optext[0] == '0') - && (optext[1] >= 'd') - && (optext[1] <= 'f')) - optext += 2; - - if (!strcmp (optext, "0.0") || !strcmp (optext, "0")) - { - regopP->n = 0x10; - return; - } - - if (!strcmp (optext, "1.0") || !strcmp (optext, "1")) - { - regopP->n = 0x16; - return; - } - } - else - { - /* Fixed point literal acceptable. */ - parse_expr (optext, &e); - if (e.X_op != O_constant - || (offs (e) < 0) || (offs (e) > 31)) - { - as_bad (_("illegal literal")); - offs (e) = 0; - } - regopP->n = offs (e); - return; - } - } - - /* Nothing worked. */ - syntax (); - regopP->mode = 0; /* Register r0 is always a good one. */ - regopP->n = 0; - regopP->special = 0; -} - -/* get_ispec: parse a memory operand for an index specification - - Here, an "index specification" is taken to be anything surrounded - by square brackets and NOT followed by anything else. - - If it's found, detach it from the input string, remove the surrounding - square brackets, and return a pointer to it. Otherwise, return NULL. */ - -static char * -get_ispec (char *textP) /* Pointer to memory operand from source instruction, no white space. */ - -{ - /* Points to start of index specification. */ - char *start; - /* Points to end of index specification. */ - char *end; - - /* Find opening square bracket, if any. */ - start = strchr (textP, '['); - - if (start != NULL) - { - /* Eliminate '[', detach from rest of operand. */ - *start++ = '\0'; - - end = strchr (start, ']'); - - if (end == NULL) - as_bad (_("unmatched '['")); - else - { - /* Eliminate ']' and make sure it was the last thing - in the string. */ - *end = '\0'; - if (*(end + 1) != '\0') - as_bad (_("garbage after index spec ignored")); - } - } - return start; -} - -/* parse_memop: parse a memory operand - - This routine is based on the observation that the 4 mode bits of the - MEMB format, taken individually, have fairly consistent meaning: - - M3 (bit 13): 1 if displacement is present (D_BIT) - M2 (bit 12): 1 for MEMB instructions (MEMB_BIT) - M1 (bit 11): 1 if index is present (I_BIT) - M0 (bit 10): 1 if abase is present (A_BIT) - - So we parse the memory operand and set bits in the mode as we find - things. Then at the end, if we go to MEMB format, we need only set - the MEMB bit (M2) and our mode is built for us. - - Unfortunately, I said "fairly consistent". The exceptions: - - DBIA - 0100 Would seem illegal, but means "abase-only". - - 0101 Would seem to mean "abase-only" -- it means IP-relative. - Must be converted to 0100. - - 0110 Would seem to mean "index-only", but is reserved. - We turn on the D bit and provide a 0 displacement. - - The other thing to observe is that we parse from the right, peeling - things * off as we go: first any index spec, then any abase, then - the displacement. */ - -static void -parse_memop (memS *memP, /* Where to put the results. */ - char *argP, /* Text of the operand to be parsed. */ - int optype) /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16. */ -{ - char *indexP; /* Pointer to index specification with "[]" removed. */ - char *p; /* Temp char pointer. */ - char iprel_flag; /* True if this is an IP-relative operand. */ - int regnum; /* Register number. */ - /* Scale factor: 1,2,4,8, or 16. Later converted to internal format - (0,1,2,3,4 respectively). */ - int scale; - int mode; /* MEMB mode bits. */ - int *intP; /* Pointer to register number. */ - - /* The following table contains the default scale factors for each - type of memory instruction. It is accessed using (optype-MEM1) - as an index -- thus it assumes the 'optype' constants are - assigned consecutive values, in the order they appear in this - table. */ - static const int def_scale[] = - { - 1, /* MEM1 */ - 2, /* MEM2 */ - 4, /* MEM4 */ - 8, /* MEM8 */ - -1, /* MEM12 -- no valid default */ - 16 /* MEM16 */ - }; - - iprel_flag = mode = 0; - - /* Any index present? */ - indexP = get_ispec (argP); - if (indexP) - { - p = strchr (indexP, '*'); - if (p == NULL) - { - /* No explicit scale -- use default for this instruction - type and assembler mode. */ - if (flag_mri) - scale = 1; - else - /* GNU960 compatibility */ - scale = def_scale[optype - MEM1]; - } - else - { - *p++ = '\0'; /* Eliminate '*' */ - - /* Now indexP->a '\0'-terminated register name, - and p->a scale factor. */ - - if (!strcmp (p, "16")) - scale = 16; - else if (strchr ("1248", *p) && (p[1] == '\0')) - scale = *p - '0'; - else - scale = -1; - } - - regnum = get_regnum (indexP); /* Get index reg. # */ - if (!IS_RG_REG (regnum)) - { - as_bad (_("invalid index register")); - return; - } - - /* Convert scale to its binary encoding. */ - switch (scale) - { - case 1: - scale = 0 << 7; - break; - case 2: - scale = 1 << 7; - break; - case 4: - scale = 2 << 7; - break; - case 8: - scale = 3 << 7; - break; - case 16: - scale = 4 << 7; - break; - default: - as_bad (_("invalid scale factor")); - return; - }; - - memP->opcode |= scale | regnum; /* Set index bits in opcode. */ - mode |= I_BIT; /* Found a valid index spec. */ - } - - /* Any abase (Register Indirect) specification present? */ - if ((p = strrchr (argP, '(')) != NULL) - { - /* "(" is there -- does it start a legal abase spec? If not, it - could be part of a displacement expression. */ - intP = (int *) hash_find (areg_hash, p); - if (intP != NULL) - { - /* Got an abase here. */ - regnum = *intP; - *p = '\0'; /* Discard register spec. */ - if (regnum == IPREL) - /* We have to special-case ip-rel mode. */ - iprel_flag = 1; - else - { - memP->opcode |= regnum << 14; - mode |= A_BIT; - } - } - } - - /* Any expression present? */ - memP->e = argP; - if (*argP != '\0') - mode |= D_BIT; - - /* Special-case ip-relative addressing. */ - if (iprel_flag) - { - if (mode & I_BIT) - syntax (); - else - { - memP->opcode |= 5 << 10; /* IP-relative mode. */ - memP->disp = 32; - } - return; - } - - /* Handle all other modes. */ - switch (mode) - { - case D_BIT | A_BIT: - /* Go with MEMA instruction format for now (grow to MEMB later - if 12 bits is not enough for the displacement). MEMA format - has a single mode bit: set it to indicate that abase is - present. */ - memP->opcode |= MEMA_ABASE; - memP->disp = 12; - break; - - case D_BIT: - /* Go with MEMA instruction format for now (grow to MEMB later - if 12 bits is not enough for the displacement). */ - memP->disp = 12; - break; - - case A_BIT: - /* For some reason, the bit string for this mode is not - consistent: it should be 0 (exclusive of the MEMB bit), so we - set it "by hand" here. */ - memP->opcode |= MEMB_BIT; - break; - - case A_BIT | I_BIT: - /* set MEMB bit in mode, and OR in mode bits. */ - memP->opcode |= mode | MEMB_BIT; - break; - - case I_BIT: - /* Treat missing displacement as displacement of 0. */ - mode |= D_BIT; - /* Fall through. */ - case D_BIT | A_BIT | I_BIT: - case D_BIT | I_BIT: - /* Set MEMB bit in mode, and OR in mode bits. */ - memP->opcode |= mode | MEMB_BIT; - memP->disp = 32; - break; - - default: - syntax (); - break; - } -} - -/* Generate a MEMA- or MEMB-format instruction. */ - -static void -mem_fmt (char *args[], /* args[0]->opcode mnemonic, args[1-3]->operands. */ - struct i960_opcode *oP,/* Pointer to description of instruction. */ - int callx) /* Is this a callx opcode. */ -{ - int i; /* Loop counter. */ - struct regop regop; /* Description of register operand. */ - char opdesc; /* Operand descriptor byte. */ - memS instr; /* Description of binary to be output. */ - char *outP; /* Where the binary was output to. */ - expressionS exp; /* Parsed expression. */ - /* ->description of deferred address fixup. */ - fixS *fixP; - -#ifdef OBJ_COFF - /* COFF support isn't in place yet for callx relaxing. */ - callx = 0; -#endif - - memset (&instr, '\0', sizeof (memS)); - instr.opcode = oP->opcode; - - /* Process operands. */ - for (i = 1; i <= oP->num_ops; i++) - { - opdesc = oP->operand[i - 1]; - - if (MEMOP (opdesc)) - parse_memop (&instr, args[i], oP->format); - else - { - parse_regop (®op, args[i], opdesc); - instr.opcode |= regop.n << 19; - } - } - - /* Parse the displacement; this must be done before emitting the - opcode, in case it is an expression using `.'. */ - parse_expr (instr.e, &exp); - - /* Output opcode. */ - outP = emit (instr.opcode); - - if (instr.disp == 0) - return; - - /* Process the displacement. */ - switch (exp.X_op) - { - case O_illegal: - as_bad (_("expression syntax error")); - break; - - case O_constant: - if (instr.disp == 32) - (void) emit (offs (exp)); /* Output displacement. */ - else - { - /* 12-bit displacement. */ - if (offs (exp) & ~0xfff) - { - /* Won't fit in 12 bits: convert already-output - instruction to MEMB format, output - displacement. */ - mema_to_memb (outP); - (void) emit (offs (exp)); - } - else - { - /* WILL fit in 12 bits: OR into opcode and - overwrite the binary we already put out. */ - instr.opcode |= offs (exp); - md_number_to_chars (outP, instr.opcode, 4); - } - } - break; - - default: - if (instr.disp == 12) - /* Displacement is dependent on a symbol, whose value - may change at link time. We HAVE to reserve 32 bits. - Convert already-output opcode to MEMB format. */ - mema_to_memb (outP); - - /* Output 0 displacement and set up address fixup for when - this symbol's value becomes known. */ - outP = emit ((long) 0); - fixP = fix_new_exp (frag_now, - outP - frag_now->fr_literal, - 4, &exp, 0, NO_RELOC); - /* Steve's linker relaxing hack. Mark this 32-bit relocation as - being in the instruction stream, specifically as part of a callx - instruction. */ - fixP->fx_bsr = callx; - break; - } -} - -/* targ_has_iclass: - - Return TRUE iff the target architecture supports the indicated - class of instructions. */ - -static int -targ_has_iclass (int ic) /* Instruction class; one of: - I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2. */ -{ - iclasses_seen |= ic; - - switch (architecture) - { - case ARCH_KA: - return ic & (I_BASE | I_KX); - case ARCH_KB: - return ic & (I_BASE | I_KX | I_FP | I_DEC); - case ARCH_MC: - return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL); - case ARCH_CA: - return ic & (I_BASE | I_CX | I_CX2 | I_CASIM); - case ARCH_JX: - return ic & (I_BASE | I_CX2 | I_JX); - case ARCH_HX: - return ic & (I_BASE | I_CX2 | I_JX | I_HX); - default: - if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL)) - && (iclasses_seen & (I_CX | I_CX2))) - { - as_warn (_("architecture of opcode conflicts with that of earlier instruction(s)")); - iclasses_seen &= ~ic; - } - return 1; - } -} - -/* shift_ok: - Determine if a "shlo" instruction can be used to implement a "ldconst". - This means that some number X < 32 can be shifted left to produce the - constant of interest. - - Return the shift count, or 0 if we can't do it. - Caller calculates X by shifting original constant right 'shift' places. */ - -static int -shift_ok (int n) /* The constant of interest. */ -{ - int shift; /* The shift count. */ - - if (n <= 0) - /* Can't do it for negative numbers. */ - return 0; - - /* Shift 'n' right until a 1 is about to be lost. */ - for (shift = 0; (n & 1) == 0; shift++) - n >>= 1; - - if (n >= 32) - return 0; - - return shift; -} - -/* parse_ldcont: - Parse and replace a 'ldconst' pseudo-instruction with an appropriate - i80960 instruction. - - Assumes the input consists of: - arg[0] opcode mnemonic ('ldconst') - arg[1] first operand (constant) - arg[2] name of register to be loaded - - Replaces opcode and/or operands as appropriate. - - Returns the new number of arguments, or -1 on failure. */ - -static int -parse_ldconst (char *arg[]) /* See above. */ -{ - int n; /* Constant to be loaded. */ - int shift; /* Shift count for "shlo" instruction. */ - static char buf[5]; /* Literal for first operand. */ - static char buf2[5]; /* Literal for second operand. */ - expressionS e; /* Parsed expression. */ - - arg[3] = NULL; /* So we can tell at the end if it got used or not. */ - - parse_expr (arg[1], &e); - switch (e.X_op) - { - default: - /* We're dependent on one or more symbols -- use "lda". */ - arg[0] = (char *) "lda"; - break; - - case O_constant: - /* Try the following mappings: - ldconst 0, -> mov 0, - ldconst 31, -> mov 31, - ldconst 32, -> addo 1,31, - ldconst 62, -> addo 31,31, - ldconst 64, -> shlo 8,3, - ldconst -1, -> subo 1,0, - ldconst -31, -> subo 31,0, - - Anything else becomes: - lda xxx,. */ - n = offs (e); - if ((0 <= n) && (n <= 31)) - arg[0] = (char *) "mov"; - else if ((-31 <= n) && (n <= -1)) - { - arg[0] = (char *) "subo"; - arg[3] = arg[2]; - sprintf (buf, "%d", -n); - arg[1] = buf; - arg[2] = (char *) "0"; - } - else if ((32 <= n) && (n <= 62)) - { - arg[0] = (char *) "addo"; - arg[3] = arg[2]; - arg[1] = (char *) "31"; - sprintf (buf, "%d", n - 31); - arg[2] = buf; - } - else if ((shift = shift_ok (n)) != 0) - { - arg[0] = (char *) "shlo"; - arg[3] = arg[2]; - sprintf (buf, "%d", shift); - arg[1] = buf; - sprintf (buf2, "%d", n >> shift); - arg[2] = buf2; - } - else - arg[0] = (char *) "lda"; - break; - - case O_illegal: - as_bad (_("invalid constant")); - return -1; - break; - } - return (arg[3] == 0) ? 2 : 3; -} - -/* reg_fmt: generate a REG-format instruction. */ - -static void -reg_fmt (char *args[], /* args[0]->opcode mnemonic, args[1-3]->operands. */ - struct i960_opcode *oP)/* Pointer to description of instruction. */ -{ - long instr; /* Binary to be output. */ - struct regop regop; /* Description of register operand. */ - int n_ops; /* Number of operands. */ - - instr = oP->opcode; - n_ops = oP->num_ops; - - if (n_ops >= 1) - { - parse_regop (®op, args[1], oP->operand[0]); - - if ((n_ops == 1) && !(instr & M3)) - { - /* 1-operand instruction in which the dst field should - be used (instead of src1). */ - regop.n <<= 19; - if (regop.special) - regop.mode = regop.special; - regop.mode <<= 13; - regop.special = 0; - } - else - { - /* regop.n goes in bit 0, needs no shifting. */ - regop.mode <<= 11; - regop.special <<= 5; - } - instr |= regop.n | regop.mode | regop.special; - } - - if (n_ops >= 2) - { - parse_regop (®op, args[2], oP->operand[1]); - - if ((n_ops == 2) && !(instr & M3)) - { - /* 2-operand instruction in which the dst field should - be used instead of src2). */ - regop.n <<= 19; - if (regop.special) - regop.mode = regop.special; - regop.mode <<= 13; - regop.special = 0; - } - else - { - regop.n <<= 14; - regop.mode <<= 12; - regop.special <<= 6; - } - instr |= regop.n | regop.mode | regop.special; - } - if (n_ops == 3) - { - parse_regop (®op, args[3], oP->operand[2]); - if (regop.special) - regop.mode = regop.special; - instr |= (regop.n <<= 19) | (regop.mode <<= 13); - } - emit (instr); -} - -/* get_args: break individual arguments out of comma-separated list - - Input assumptions: - - all comments and labels have been removed - - all strings of whitespace have been collapsed to a single blank. - - all character constants ('x') have been replaced with decimal - - Output: - args[0] is untouched. args[1] points to first operand, etc. All args: - - are NULL-terminated - - contain no whitespace - - Return value: - Number of operands (0,1,2, or 3) or -1 on error. */ - -static int -get_args (char *p, /* Pointer to comma-separated operands; Mucked by us. */ - char *args[]) /* Output arg: pointers to operands placed in args[1-3]. - Must accommodate 4 entries (args[0-3]). */ - -{ - int n; /* Number of operands. */ - char *to; - - /* Skip lead white space. */ - while (*p == ' ') - p++; - - if (*p == '\0') - return 0; - - n = 1; - args[1] = p; - - /* Squeeze blanks out by moving non-blanks toward start of string. - Isolate operands, whenever comma is found. */ - to = p; - while (*p != '\0') - { - if (*p == ' ' - && (! ISALNUM (p[1]) - || ! ISALNUM (p[-1]))) - p++; - else if (*p == ',') - { - /* Start of operand. */ - if (n == 3) - { - as_bad (_("too many operands")); - return -1; - } - *to++ = '\0'; /* Terminate argument. */ - args[++n] = to; /* Start next argument. */ - p++; - } - else - *to++ = *p++; - } - *to = '\0'; - return n; -} - -/* i_scan: perform lexical scan of ascii assembler instruction. - - Input assumptions: - - input string is an i80960 instruction (not a pseudo-op) - - all comments and labels have been removed - - all strings of whitespace have been collapsed to a single blank. - - Output: - args[0] points to opcode, other entries point to operands. All strings: - - are NULL-terminated - - contain no whitespace - - have character constants ('x') replaced with a decimal number - - Return value: - Number of operands (0,1,2, or 3) or -1 on error. */ - -static int -i_scan (char *iP, /* Pointer to ascii instruction; Mucked by us. */ - char *args[]) /* Output arg: pointers to opcode and operands placed here. - Must accommodate 4 entries. */ -{ - /* Isolate opcode. */ - if (*(iP) == ' ') - iP++; - - args[0] = iP; - for (; *iP != ' '; iP++) - { - if (*iP == '\0') - { - /* There are no operands. */ - if (args[0] == iP) - { - /* We never moved: there was no opcode either! */ - as_bad (_("missing opcode")); - return -1; - } - return 0; - } - } - *iP++ = '\0'; - return (get_args (iP, args)); -} - -static void -brcnt_emit (void) -{ - /* Emit call to "increment" routine. */ - ctrl_fmt (BR_CNT_FUNC, CALL, 1); - /* Emit inline counter to be incremented. */ - emit (0); -} - -static char * -brlab_next (void) -{ - static char buf[20]; - - sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++); - return buf; -} - -static void -ctrl_fmt (const char *targP, /* Pointer to text of lone operand (if any). */ - long opcode, /* Template of instruction. */ - int num_ops) /* Number of operands. */ -{ - int instrument; /* TRUE iff we should add instrumentation to track - how often the branch is taken. */ - - if (num_ops == 0) - emit (opcode); /* Output opcode. */ - else - { - instrument = instrument_branches && (opcode != CALL) - && (opcode != B) && (opcode != RET) && (opcode != BAL); - - if (instrument) - { - brcnt_emit (); - colon (brlab_next ()); - } - - /* The operand MUST be an ip-relative displacement. Parse it - and set up address fix for the instruction we just output. */ - get_cdisp (targP, "CTRL", opcode, 24, 0, 0); - - if (instrument) - brcnt_emit (); - } -} - -static void -cobr_fmt (/* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */ - char *arg[], - /* Opcode, with branch-prediction bits already set if necessary. */ - long opcode, - /* Pointer to description of instruction. */ - struct i960_opcode *oP) -{ - long instr; /* 32-bit instruction. */ - struct regop regop; /* Description of register operand. */ - int n; /* Number of operands. */ - int var_frag; /* 1 if varying length code fragment should - be emitted; 0 if an address fix - should be emitted. */ - - instr = opcode; - n = oP->num_ops; - - if (n >= 1) - { - /* First operand (if any) of a COBR is always a register - operand. Parse it. */ - parse_regop (®op, arg[1], oP->operand[0]); - instr |= (regop.n << 19) | (regop.mode << 13); - } - - if (n >= 2) - { - /* Second operand (if any) of a COBR is always a register - operand. Parse it. */ - parse_regop (®op, arg[2], oP->operand[1]); - instr |= (regop.n << 14) | regop.special; - } - - if (n < 3) - emit (instr); - else - { - if (instrument_branches) - { - brcnt_emit (); - colon (brlab_next ()); - } - - /* A third operand to a COBR is always a displacement. Parse - it; if it's relaxable (a cobr "j" directive, or any cobr - other than bbs/bbc when the "-norelax" option is not in use) - set up a variable code fragment; otherwise set up an address - fix. */ - var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */ - get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0); - - if (instrument_branches) - brcnt_emit (); - } -} - -/* Assumptions about the passed-in text: - - all comments, labels removed - - text is an instruction - - all white space compressed to single blanks - - all character constants have been replaced with decimal. */ - -void -md_assemble (char *textP) -{ - /* Parsed instruction text, containing NO whitespace: arg[0]->opcode - mnemonic arg[1-3]->operands, with char constants replaced by - decimal numbers. */ - char *args[4]; - /* Number of instruction operands. */ - int n_ops; - /* Pointer to instruction description. */ - struct i960_opcode *oP; - /* TRUE iff opcode mnemonic included branch-prediction suffix (".f" - or ".t"). */ - int branch_predict; - /* Setting of branch-prediction bit(s) to be OR'd into instruction - opcode of CTRL/COBR format instructions. */ - long bp_bits; - /* Offset of last character in opcode mnemonic. */ - int n; - const char *bp_error_msg = _("branch prediction invalid on this opcode"); - - /* Parse instruction into opcode and operands. */ - memset (args, '\0', sizeof (args)); - - n_ops = i_scan (textP, args); - - if (n_ops == -1) - return; /* Error message already issued. */ - - /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction. */ - if (!strcmp (args[0], "ldconst")) - { - n_ops = parse_ldconst (args); - if (n_ops == -1) - return; - } - - /* Check for branch-prediction suffix on opcode mnemonic, strip it off. */ - n = strlen (args[0]) - 1; - branch_predict = 0; - bp_bits = 0; - - if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f')) - { - /* We could check here to see if the target architecture - supports branch prediction, but why bother? The bit will - just be ignored by processors that don't use it. */ - branch_predict = 1; - bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN; - args[0][n - 1] = '\0'; /* Strip suffix from opcode mnemonic */ - } - - /* Look up opcode mnemonic in table and check number of operands. - Check that opcode is legal for the target architecture. If all - looks good, assemble instruction. */ - oP = (struct i960_opcode *) hash_find (op_hash, args[0]); - if (!oP || !targ_has_iclass (oP->iclass)) - as_bad (_("invalid opcode, \"%s\"."), args[0]); - else if (n_ops != oP->num_ops) - as_bad (_("improper number of operands. Expecting %d, got %d"), - oP->num_ops, n_ops); - else - { - switch (oP->format) - { - case FBRA: - case CTRL: - ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops); - if (oP->format == FBRA) - /* Now generate a 'bno' to same arg */ - ctrl_fmt (args[1], BNO | bp_bits, 1); - break; - case COBR: - case COJ: - cobr_fmt (args, oP->opcode | bp_bits, oP); - break; - case REG: - if (branch_predict) - as_warn ("%s", bp_error_msg); - reg_fmt (args, oP); - break; - case MEM1: - if (args[0][0] == 'c' && args[0][1] == 'a') - { - if (branch_predict) - as_warn ("%s", bp_error_msg); - mem_fmt (args, oP, 1); - break; - } - /* Fall through. */ - case MEM2: - case MEM4: - case MEM8: - case MEM12: - case MEM16: - if (branch_predict) - as_warn ("%s", bp_error_msg); - mem_fmt (args, oP, 0); - break; - case CALLJ: - if (branch_predict) - as_warn ("%s", bp_error_msg); - /* Output opcode & set up "fixup" (relocation); flag - relocation as 'callj' type. */ - know (oP->num_ops == 1); - get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1); - break; - default: - BAD_CASE (oP->format); - break; - } - } -} - -void -md_number_to_chars (char *buf, - valueT value, - int n) -{ - number_to_chars_littleendian (buf, value, n); -} - -const char * -md_atof (int type, char *litP, int *sizeP) -{ - return ieee_md_atof (type, litP, sizeP, FALSE); -} - -static void -md_number_to_imm (char *buf, long val, int n) -{ - md_number_to_chars (buf, val, n); -} - -static void -md_number_to_field (char *instrP, /* Pointer to instruction to be fixed. */ - long val, /* Address fixup value. */ - bit_fixS *bfixP) /* Description of bit field to be fixed up. */ -{ - int numbits; /* Length of bit field to be fixed. */ - long instr; /* 32-bit instruction to be fixed-up. */ - long sign; /* 0 or -1, according to sign bit of 'val'. */ - - /* Convert instruction back to host byte order. */ - instr = md_chars_to_number (instrP, 4); - - /* Surprise! -- we stored the number of bits to be modified rather - than a pointer to a structure. */ - numbits = (int) (size_t) bfixP; - if (numbits == 1) - /* This is a no-op, stuck here by reloc_callj(). */ - return; - - know ((numbits == 13) || (numbits == 24)); - - /* Propagate sign bit of 'val' for the given number of bits. Result - should be all 0 or all 1. */ - sign = val >> ((int) numbits - 1); - if (((val < 0) && (sign != -1)) - || ((val > 0) && (sign != 0))) - as_bad (_("Fixup of %ld too large for field width of %d"), - val, numbits); - else - { - /* Put bit field into instruction and write back in target - * byte order. */ - val &= ~(-(1 << (int) numbits)); /* Clear unused sign bits. */ - instr |= val; - md_number_to_chars (instrP, instr, 4); - } -} - - -/* md_parse_option - Invocation line includes a switch not recognized by the base assembler. - See if it's a processor-specific option. For the 960, these are: - - -norelax: - Conditional branch instructions that require displacements - greater than 13 bits (or that have external targets) should - generate errors. The default is to replace each such - instruction with the corresponding compare (or chkbit) and - branch instructions. Note that the Intel "j" cobr directives - are ALWAYS "de-optimized" in this way when necessary, - regardless of the setting of this option. - - -b: - Add code to collect information about branches taken, for - later optimization of branch prediction bits by a separate - tool. COBR and CNTL format instructions have branch - prediction bits (in the CX architecture); if "BR" represents - an instruction in one of these classes, the following rep- - resents the code generated by the assembler: - - call - .word 0 # pre-counter - Label: BR - call - .word 0 # post-counter - - A table of all such "Labels" is also generated. - - -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA: - Select the 80960 architecture. Instructions or features not - supported by the selected architecture cause fatal errors. - The default is to generate code for any instruction or feature - that is supported by SOME version of the 960 (even if this - means mixing architectures!). */ - -const char *md_shortopts = "A:b"; -struct option md_longopts[] = -{ -#define OPTION_LINKRELAX (OPTION_MD_BASE) - {"linkrelax", no_argument, NULL, OPTION_LINKRELAX}, - {"link-relax", no_argument, NULL, OPTION_LINKRELAX}, -#define OPTION_NORELAX (OPTION_MD_BASE + 1) - {"norelax", no_argument, NULL, OPTION_NORELAX}, - {"no-relax", no_argument, NULL, OPTION_NORELAX}, - {NULL, no_argument, NULL, 0} -}; -size_t md_longopts_size = sizeof (md_longopts); - -struct tabentry -{ - const char *flag; - int arch; -}; -static const struct tabentry arch_tab[] = -{ - {"KA", ARCH_KA}, - {"KB", ARCH_KB}, - {"SA", ARCH_KA}, /* Synonym for KA. */ - {"SB", ARCH_KB}, /* Synonym for KB. */ - {"KC", ARCH_MC}, /* Synonym for MC. */ - {"MC", ARCH_MC}, - {"CA", ARCH_CA}, - {"JX", ARCH_JX}, - {"HX", ARCH_HX}, - {NULL, 0} -}; - -int -md_parse_option (int c, const char *arg) -{ - switch (c) - { - case OPTION_LINKRELAX: - linkrelax = 1; - flag_keep_locals = 1; - break; - - case OPTION_NORELAX: - norelax = 1; - break; - - case 'b': - instrument_branches = 1; - break; - - case 'A': - { - const struct tabentry *tp; - const char *p = arg; - - for (tp = arch_tab; tp->flag != NULL; tp++) - if (!strcmp (p, tp->flag)) - break; - - if (tp->flag == NULL) - { - as_bad (_("invalid architecture %s"), p); - return 0; - } - else - architecture = tp->arch; - } - break; - - default: - return 0; - } - - return 1; -} - -void -md_show_usage (FILE *stream) -{ - int i; - - fprintf (stream, _("I960 options:\n")); - for (i = 0; arch_tab[i].flag; i++) - fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag); - fprintf (stream, _("\n\ - specify variant of 960 architecture\n\ --b add code to collect statistics about branches taken\n\ --link-relax preserve individual alignment directives so linker\n\ - can do relaxing (b.out format only)\n\ --no-relax don't alter compare-and-branch instructions for\n\ - long displacements\n")); -} - -/* relax_cobr: - Replace cobr instruction in a code fragment with equivalent branch and - compare instructions, so it can reach beyond a 13-bit displacement. - Set up an address fix/relocation for the new branch instruction. */ - -/* This "conditional jump" table maps cobr instructions into - equivalent compare and branch opcodes. */ - -static const -struct -{ - long compare; - long branch; -} - -coj[] = -{ /* COBR OPCODE: */ - { CHKBIT, BNO }, /* 0x30 - bbc */ - { CMPO, BG }, /* 0x31 - cmpobg */ - { CMPO, BE }, /* 0x32 - cmpobe */ - { CMPO, BGE }, /* 0x33 - cmpobge */ - { CMPO, BL }, /* 0x34 - cmpobl */ - { CMPO, BNE }, /* 0x35 - cmpobne */ - { CMPO, BLE }, /* 0x36 - cmpoble */ - { CHKBIT, BO }, /* 0x37 - bbs */ - { CMPI, BNO }, /* 0x38 - cmpibno */ - { CMPI, BG }, /* 0x39 - cmpibg */ - { CMPI, BE }, /* 0x3a - cmpibe */ - { CMPI, BGE }, /* 0x3b - cmpibge */ - { CMPI, BL }, /* 0x3c - cmpibl */ - { CMPI, BNE }, /* 0x3d - cmpibne */ - { CMPI, BLE }, /* 0x3e - cmpible */ - { CMPI, BO }, /* 0x3f - cmpibo */ -}; - -static void -relax_cobr (fragS *fragP) /* fragP->fr_opcode is assumed to point to - the cobr instruction, which comes at the - end of the code fragment. */ -{ - int opcode, src1, src2, m1, s2; - /* Bit fields from cobr instruction. */ - long bp_bits; /* Branch prediction bits from cobr instruction. */ - long instr; /* A single i960 instruction. */ - /* ->instruction to be replaced. */ - char *iP; - fixS *fixP; /* Relocation that can be done at assembly time. */ - - /* Pick up & parse cobr instruction. */ - iP = fragP->fr_opcode; - instr = md_chars_to_number (iP, 4); - opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index. */ - src1 = (instr >> 19) & 0x1f; - m1 = (instr >> 13) & 1; - s2 = instr & 1; - src2 = (instr >> 14) & 0x1f; - bp_bits = instr & BP_MASK; - - /* Generate and output compare instruction. */ - instr = coj[opcode].compare - | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14); - md_number_to_chars (iP, instr, 4); - - /* Output branch instruction. */ - md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4); - - /* Set up address fixup/relocation. */ - fixP = fix_new (fragP, - iP + 4 - fragP->fr_literal, - 4, - fragP->fr_symbol, - fragP->fr_offset, - 1, - NO_RELOC); - - fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field. */ - - fragP->fr_fix += 4; - frag_wane (fragP); -} - -/* md_convert_frag: - - Called by base assembler after address relaxation is finished: modify - variable fragments according to how much relaxation was done. - - If the fragment substate is still 1, a 13-bit displacement was enough - to reach the symbol in question. Set up an address fixup, but otherwise - leave the cobr instruction alone. - - If the fragment substate is 2, a 13-bit displacement was not enough. - Replace the cobr with a two instructions (a compare and a branch). */ - -void -md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, - segT sec ATTRIBUTE_UNUSED, - fragS *fragP) -{ - /* Structure describing needed address fix. */ - fixS *fixP; - - switch (fragP->fr_subtype) - { - case 1: - /* Leave single cobr instruction. */ - fixP = fix_new (fragP, - fragP->fr_opcode - fragP->fr_literal, - 4, - fragP->fr_symbol, - fragP->fr_offset, - 1, - NO_RELOC); - - fixP->fx_bit_fixP = (bit_fixS *) 13; /* Size of bit field. */ - break; - case 2: - /* Replace cobr with compare/branch instructions. */ - relax_cobr (fragP); - break; - default: - BAD_CASE (fragP->fr_subtype); - break; - } -} - -/* md_estimate_size_before_relax: How much does it look like *fragP will grow? - - Called by base assembler just before address relaxation. - Return the amount by which the fragment will grow. - - Any symbol that is now undefined will not become defined; cobr's - based on undefined symbols will have to be replaced with a compare - instruction and a branch instruction, and the code fragment will grow - by 4 bytes. */ - -int -md_estimate_size_before_relax (fragS *fragP, segT segment_type) -{ - /* If symbol is undefined in this segment, go to "relaxed" state - (compare and branch instructions instead of cobr) right now. */ - if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type) - { - relax_cobr (fragP); - return 4; - } - - return md_relax_table[fragP->fr_subtype].rlx_length; -} - -#if defined(OBJ_AOUT) | defined(OBJ_BOUT) - -/* md_ri_to_chars: - This routine exists in order to overcome machine byte-order problems - when dealing with bit-field entries in the relocation_info struct. - - But relocation info will be used on the host machine only (only - executable code is actually downloaded to the i80960). Therefore, - we leave it in host byte order. */ - -static void -md_ri_to_chars (char *where, struct relocation_info *ri) -{ - host_number_to_chars (where, ri->r_address, 4); - host_number_to_chars (where + 4, ri->r_index, 3); -#if WORDS_BIGENDIAN - where[7] = (ri->r_pcrel << 7 - | ri->r_length << 5 - | ri->r_extern << 4 - | ri->r_bsr << 3 - | ri->r_disp << 2 - | ri->r_callj << 1 - | ri->nuthin << 0); -#else - where[7] = (ri->r_pcrel << 0 - | ri->r_length << 1 - | ri->r_extern << 3 - | ri->r_bsr << 4 - | ri->r_disp << 5 - | ri->r_callj << 6 - | ri->nuthin << 7); -#endif -} - -#endif /* defined(OBJ_AOUT) | defined(OBJ_BOUT) */ - - -/* brtab_emit: generate the fetch-prediction branch table. - - See the comments above the declaration of 'br_cnt' for details on - branch-prediction instrumentation. - - The code emitted here would be functionally equivalent to the following - example assembler source. - - .data - .align 2 - BR_TAB_NAME: - .word 0 # link to next table - .word 3 # length of table - .word LBRANCH0 # 1st entry in table proper - .word LBRANCH1 - .word LBRANCH2 */ - -void -brtab_emit (void) -{ - int i; - char buf[20]; - /* Where the binary was output to. */ - char *p; - - if (!instrument_branches) - return; - - subseg_set (data_section, 0); /* .data */ - frag_align (2, 0, 0); /* .align 2 */ - record_alignment (now_seg, 2); - colon (BR_TAB_NAME); /* BR_TAB_NAME: */ - emit (0); /* .word 0 #link to next table */ - emit (br_cnt); /* .word n #length of table */ - - for (i = 0; i < br_cnt; i++) - { - sprintf (buf, "%s%d", BR_LABEL_BASE, i); - p = emit (0); - fix_new (frag_now, - p - frag_now->fr_literal, - 4, symbol_find (buf), 0, 0, NO_RELOC); - } -} - -/* s_leafproc: process .leafproc pseudo-op - - .leafproc takes two arguments, the second one is optional: - arg[1]: name of 'call' entry point to leaf procedure - arg[2]: name of 'bal' entry point to leaf procedure - - If the two arguments are identical, or if the second one is missing, - the first argument is taken to be the 'bal' entry point. - - If there are 2 distinct arguments, we must make sure that the 'bal' - entry point immediately follows the 'call' entry point in the linked - list of symbols. */ - -static void -s_leafproc (int n_ops, /* Number of operands. */ - char *args[]) /* args[1]->1st operand, args[2]->2nd operand. */ -{ - symbolS *callP; /* Pointer to leafproc 'call' entry point symbol. */ - symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol. */ - - if ((n_ops != 1) && (n_ops != 2)) - { - as_bad (_("should have 1 or 2 operands")); - return; - } - - /* Find or create symbol for 'call' entry point. */ - callP = symbol_find_or_make (args[1]); - - if (TC_S_IS_CALLNAME (callP)) - as_warn (_("Redefining leafproc %s"), S_GET_NAME (callP)); - - /* If that was the only argument, use it as the 'bal' entry point. - Otherwise, mark it as the 'call' entry point and find or create - another symbol for the 'bal' entry point. */ - if ((n_ops == 1) || !strcmp (args[1], args[2])) - { - TC_S_FORCE_TO_BALNAME (callP); - } - else - { - TC_S_FORCE_TO_CALLNAME (callP); - - balP = symbol_find_or_make (args[2]); - if (TC_S_IS_CALLNAME (balP)) - as_warn (_("Redefining leafproc %s"), S_GET_NAME (balP)); - - TC_S_FORCE_TO_BALNAME (balP); - -#ifndef OBJ_ELF - tc_set_bal_of_call (callP, balP); -#endif - } -} - -/* s_sysproc: process .sysproc pseudo-op - - .sysproc takes two arguments: - arg[1]: name of entry point to system procedure - arg[2]: 'entry_num' (index) of system procedure in the range - [0,31] inclusive. - - For [ab].out, we store the 'entrynum' in the 'n_other' field of - the symbol. Since that entry is normally 0, we bias 'entrynum' - by adding 1 to it. It must be unbiased before it is used. */ - -static void -s_sysproc (int n_ops, /* Number of operands. */ - char *args[]) /* args[1]->1st operand, args[2]->2nd operand. */ -{ - expressionS exp; - symbolS *symP; - - if (n_ops != 2) - { - as_bad (_("should have two operands")); - return; - } - - /* Parse "entry_num" argument and check it for validity. */ - parse_expr (args[2], &exp); - if (exp.X_op != O_constant - || (offs (exp) < 0) - || (offs (exp) > 31)) - { - as_bad (_("'entry_num' must be absolute number in [0,31]")); - return; - } - - /* Find/make symbol and stick entry number (biased by +1) into it. */ - symP = symbol_find_or_make (args[1]); - - if (TC_S_IS_SYSPROC (symP)) - as_warn (_("Redefining entrynum for sysproc %s"), S_GET_NAME (symP)); - - TC_S_SET_SYSPROC (symP, offs (exp)); /* Encode entry number. */ - TC_S_FORCE_TO_SYSPROC (symP); -} - -/* parse_po: parse machine-dependent pseudo-op - - This is a top-level routine for machine-dependent pseudo-ops. It slurps - up the rest of the input line, breaks out the individual arguments, - and dispatches them to the correct handler. */ - -static void -parse_po (int po_num) /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC. */ -{ - /* Pointers operands, with no embedded whitespace. - arg[0] unused, arg[1-3]->operands. */ - char *args[4]; - int n_ops; /* Number of operands. */ - char *p; /* Pointer to beginning of unparsed argument string. */ - char eol; /* Character that indicated end of line. */ - - extern char is_end_of_line[]; - - /* Advance input pointer to end of line. */ - p = input_line_pointer; - while (!is_end_of_line[(unsigned char) *input_line_pointer]) - input_line_pointer++; - - eol = *input_line_pointer; /* Save end-of-line char. */ - *input_line_pointer = '\0'; /* Terminate argument list. */ - - /* Parse out operands. */ - n_ops = get_args (p, args); - if (n_ops == -1) - return; - - /* Dispatch to correct handler. */ - switch (po_num) - { - case S_SYSPROC: - s_sysproc (n_ops, args); - break; - case S_LEAFPROC: - s_leafproc (n_ops, args); - break; - default: - BAD_CASE (po_num); - break; - } - - /* Restore eol, so line numbers get updated correctly. Base - assembler assumes we leave input pointer pointing at char - following the eol. */ - *input_line_pointer++ = eol; -} - -/* reloc_callj: Relocate a 'callj' instruction - - This is a "non-(GNU)-standard" machine-dependent hook. The base - assembler calls it when it decides it can relocate an address at - assembly time instead of emitting a relocation directive. - - Check to see if the relocation involves a 'callj' instruction to a: - sysproc: Replace the default 'call' instruction with a 'calls' - leafproc: Replace the default 'call' instruction with a 'bal'. - other proc: Do nothing. - - See b.out.h for details on the 'n_other' field in a symbol structure. - - IMPORTANT!: - Assumes the caller has already figured out, in the case of a leafproc, - to use the 'bal' entry point, and has substituted that symbol into the - passed fixup structure. */ - -int -reloc_callj (fixS *fixP) /* Relocation that can be done at assembly time. */ -{ - /* Points to the binary for the instruction being relocated. */ - char *where; - - if (!fixP->fx_tcbit) - /* This wasn't a callj instruction in the first place. */ - return 0; - - where = fixP->fx_frag->fr_literal + fixP->fx_where; - - if (TC_S_IS_SYSPROC (fixP->fx_addsy)) - { - /* Symbol is a .sysproc: replace 'call' with 'calls'. System - procedure number is (other-1). */ - md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4); - - /* Nothing else needs to be done for this instruction. Make - sure 'md_number_to_field()' will perform a no-op. */ - fixP->fx_bit_fixP = (bit_fixS *) 1; - } - else if (TC_S_IS_CALLNAME (fixP->fx_addsy)) - { - /* Should not happen: see block comment above. */ - as_fatal (_("Trying to 'bal' to %s"), S_GET_NAME (fixP->fx_addsy)); - } - else if (TC_S_IS_BALNAME (fixP->fx_addsy)) - { - /* Replace 'call' with 'bal'; both instructions have the same - format, so calling code should complete relocation as if - nothing happened here. */ - md_number_to_chars (where, BAL, 4); - } - else if (TC_S_IS_BADPROC (fixP->fx_addsy)) - as_bad (_("Looks like a proc, but can't tell what kind.\n")); - - /* Otherwise Symbol is neither a sysproc nor a leafproc. */ - return 0; -} - -/* Handle the MRI .endian pseudo-op. */ - -static void -s_endian (int ignore ATTRIBUTE_UNUSED) -{ - char *name; - char c; - - c = get_symbol_name (&name); - if (strcasecmp (name, "little") == 0) - ; - else if (strcasecmp (name, "big") == 0) - as_bad (_("big endian mode is not supported")); - else - as_warn (_("ignoring unrecognized .endian type `%s'"), name); - - (void) restore_line_pointer (c); - - demand_empty_rest_of_line (); -} - -/* We have no need to default values of symbols. */ - -symbolS * -md_undefined_symbol (char *name ATTRIBUTE_UNUSED) -{ - return 0; -} - -/* Exactly what point is a PC-relative offset relative TO? - On the i960, they're relative to the address of the instruction, - which we have set up as the address of the fixup too. */ -long -md_pcrel_from (fixS *fixP) -{ - return fixP->fx_where + fixP->fx_frag->fr_address; -} - -void -md_apply_fix (fixS *fixP, - valueT *valP, - segT seg ATTRIBUTE_UNUSED) -{ - long val = *valP; - char *place = fixP->fx_where + fixP->fx_frag->fr_literal; - - if (!fixP->fx_bit_fixP) - { - md_number_to_imm (place, val, fixP->fx_size); - } - else if ((int) (size_t) fixP->fx_bit_fixP == 13 - && fixP->fx_addsy != NULL - && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section) - { - /* This is a COBR instruction. They have only a - 13-bit displacement and are only to be used - for local branches: flag as error, don't generate - relocation. */ - as_bad_where (fixP->fx_file, fixP->fx_line, - _("can't use COBR format with external label")); - fixP->fx_addsy = NULL; - } - else - md_number_to_field (place, val, fixP->fx_bit_fixP); - - if (fixP->fx_addsy == NULL) - fixP->fx_done = 1; -} - -#if defined(OBJ_AOUT) | defined(OBJ_BOUT) -void -tc_bout_fix_to_chars (char *where, - fixS *fixP, - relax_addressT segment_address_in_file) -{ - static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; - struct relocation_info ri; - symbolS *symbolP; - - memset ((char *) &ri, '\0', sizeof (ri)); - symbolP = fixP->fx_addsy; - know (symbolP != 0 || fixP->fx_r_type != NO_RELOC); - ri.r_bsr = fixP->fx_bsr; /*SAC LD RELAX HACK */ - /* These two 'cuz of NS32K */ - ri.r_callj = fixP->fx_tcbit; - if (fixP->fx_bit_fixP) - ri.r_length = 2; - else - ri.r_length = nbytes_r_length[fixP->fx_size]; - ri.r_pcrel = fixP->fx_pcrel; - ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file; - - if (fixP->fx_r_type != NO_RELOC) - { - switch (fixP->fx_r_type) - { - case rs_align: - ri.r_index = -2; - ri.r_pcrel = 1; - ri.r_length = fixP->fx_size - 1; - break; - case rs_org: - ri.r_index = -2; - ri.r_pcrel = 0; - break; - case rs_fill: - ri.r_index = -1; - break; - default: - abort (); - } - ri.r_extern = 0; - } - else if (linkrelax || !S_IS_DEFINED (symbolP) || fixP->fx_bsr) - { - ri.r_extern = 1; - ri.r_index = symbolP->sy_number; - } - else - { - ri.r_extern = 0; - ri.r_index = S_GET_TYPE (symbolP); - } - - /* Output the relocation information in machine-dependent form. */ - md_ri_to_chars (where, &ri); -} - -#endif /* OBJ_AOUT or OBJ_BOUT */ - -/* Align an address by rounding it up to the specified boundary. */ - -valueT -md_section_align (segT seg, - valueT addr) /* Address to be rounded up. */ -{ - int align; - - align = bfd_get_section_alignment (stdoutput, seg); - return (addr + (1 << align) - 1) & -(1 << align); -} - -extern int coff_flags; - -/* For aout or bout, the bal immediately follows the call. - - For coff, we cheat and store a pointer to the bal symbol in the - second aux entry of the call. */ - -#undef OBJ_ABOUT -#ifdef OBJ_AOUT -#define OBJ_ABOUT -#endif -#ifdef OBJ_BOUT -#define OBJ_ABOUT -#endif - -void -tc_set_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED, - symbolS *balP ATTRIBUTE_UNUSED) -{ - know (TC_S_IS_CALLNAME (callP)); - know (TC_S_IS_BALNAME (balP)); - -#ifdef OBJ_COFF - - callP->sy_tc = balP; - S_SET_NUMBER_AUXILIARY (callP, 2); - -#else /* ! OBJ_COFF */ -#ifdef OBJ_ABOUT - - /* If the 'bal' entry doesn't immediately follow the 'call' - symbol, unlink it from the symbol list and re-insert it. */ - if (symbol_next (callP) != balP) - { - symbol_remove (balP, &symbol_rootP, &symbol_lastP); - symbol_append (balP, callP, &symbol_rootP, &symbol_lastP); - } /* if not in order */ - -#else /* ! OBJ_ABOUT */ - as_fatal ("Only supported for a.out, b.out, or COFF"); -#endif /* ! OBJ_ABOUT */ -#endif /* ! OBJ_COFF */ -} - -symbolS * -tc_get_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED) -{ - symbolS *retval; - - know (TC_S_IS_CALLNAME (callP)); - -#ifdef OBJ_COFF - retval = callP->sy_tc; -#else -#ifdef OBJ_ABOUT - retval = symbol_next (callP); -#else - as_fatal ("Only supported for a.out, b.out, or COFF"); -#endif /* ! OBJ_ABOUT */ -#endif /* ! OBJ_COFF */ - - know (TC_S_IS_BALNAME (retval)); - return retval; -} - -#ifdef OBJ_COFF -void -tc_coff_symbol_emit_hook (symbolS *symbolP ATTRIBUTE_UNUSED) -{ - if (TC_S_IS_CALLNAME (symbolP)) - { - symbolS *balP = tc_get_bal_of_call (symbolP); - - symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP); - if (S_GET_STORAGE_CLASS (symbolP) == C_EXT) - S_SET_STORAGE_CLASS (symbolP, C_LEAFEXT); - else - S_SET_STORAGE_CLASS (symbolP, C_LEAFSTAT); - S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT)); - /* Fix up the bal symbol. */ - S_SET_STORAGE_CLASS (balP, C_LABEL); - } -} -#endif /* OBJ_COFF */ - -void -i960_handle_align (fragS *fragp ATTRIBUTE_UNUSED) -{ - if (!linkrelax) - return; - -#ifndef OBJ_BOUT - as_bad (_("option --link-relax is only supported in b.out format")); - linkrelax = 0; - return; -#else - - /* The text section "ends" with another alignment reloc, to which we - aren't adding padding. */ - if (fragp->fr_next == text_last_frag - || fragp->fr_next == data_last_frag) - return; - - /* alignment directive */ - fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0, - (int) fragp->fr_type); -#endif /* OBJ_BOUT */ -} - -int -i960_validate_fix (fixS *fixP, segT this_segment_type ATTRIBUTE_UNUSED) -{ - if (fixP->fx_tcbit && TC_S_IS_CALLNAME (fixP->fx_addsy)) - { - /* Relocation should be done via the associated 'bal' - entry point symbol. */ - if (!TC_S_IS_BALNAME (tc_get_bal_of_call (fixP->fx_addsy))) - { - as_bad_where (fixP->fx_file, fixP->fx_line, - _("No 'bal' entry point for leafproc %s"), - S_GET_NAME (fixP->fx_addsy)); - return 0; - } - fixP->fx_addsy = tc_get_bal_of_call (fixP->fx_addsy); - } - - return 1; -} - -/* From cgen.c: */ - -static short -tc_bfd_fix2rtype (fixS *fixP) -{ - if (fixP->fx_pcrel == 0 && fixP->fx_size == 4) - return BFD_RELOC_32; - - if (fixP->fx_pcrel != 0 && fixP->fx_size == 4) - return BFD_RELOC_24_PCREL; - - abort (); - return 0; -} - -/* Translate internal representation of relocation info to BFD target - format. - - FIXME: To what extent can we get all relevant targets to use this? */ - -arelent * -tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP) -{ - arelent * reloc; - - reloc = XNEW (arelent); - - /* HACK: Is this right? */ - fixP->fx_r_type = tc_bfd_fix2rtype (fixP); - - reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); - if (reloc->howto == NULL) - { - as_bad_where (fixP->fx_file, fixP->fx_line, - _("internal error: can't export reloc type %d (`%s')"), - fixP->fx_r_type, - bfd_get_reloc_code_name (fixP->fx_r_type)); - return NULL; - } - - gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative); - - reloc->sym_ptr_ptr = XNEW (asymbol *); - *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); - reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; - reloc->addend = fixP->fx_addnumber; - - return reloc; -} - -/* end from cgen.c */ - -const pseudo_typeS md_pseudo_table[] = -{ - {"bss", s_lcomm, 1}, - {"endian", s_endian, 0}, - {"extended", float_cons, 't'}, - {"leafproc", parse_po, S_LEAFPROC}, - {"sysproc", parse_po, S_SYSPROC}, - - {"word", cons, 4}, - {"quad", cons, 16}, - - {0, 0, 0} -}; diff --git a/gas/config/tc-i960.h b/gas/config/tc-i960.h deleted file mode 100644 index 9c71150..0000000 --- a/gas/config/tc-i960.h +++ /dev/null @@ -1,185 +0,0 @@ -/* tc-i960.h - Basic 80960 instruction formats. - Copyright (C) 1989-2018 Free Software Foundation, Inc. - - This file is part of GAS, the GNU Assembler. - - GAS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GAS is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS; see the file COPYING. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -#ifndef TC_I960 -#define TC_I960 1 - -#ifdef OBJ_ELF -#define TARGET_FORMAT "elf32-i960" -#define TARGET_ARCH bfd_arch_i960 -#endif - -#define TARGET_BYTES_BIG_ENDIAN 0 - -#define WORKING_DOT_WORD - -/* - * The 'COJ' instructions are actually COBR instructions with the 'b' in - * the mnemonic replaced by a 'j'; they are ALWAYS "de-optimized" if necessary: - * if the displacement will not fit in 13 bits, the assembler will replace them - * with the corresponding compare and branch instructions. - * - * All of the 'MEMn' instructions are the same format; the 'n' in the name - * indicates the default index scale factor (the size of the datum operated on). - * - * The FBRA formats are not actually an instruction format. They are the - * "convenience directives" for branching on floating-point comparisons, - * each of which generates 2 instructions (a 'bno' and one other branch). - * - * The CALLJ format is not actually an instruction format. It indicates that - * the instruction generated (a CTRL-format 'call') should have its relocation - * specially flagged for link-time replacement with a 'bal' or 'calls' if - * appropriate. - */ - -/* tailor gas */ -#define LOCAL_LABELS_FB 1 -#define BITFIELD_CONS_EXPRESSIONS - -/* tailor the coff format */ -#define COFF_MAGIC I960ROMAGIC -#define OBJ_COFF_MAX_AUXENTRIES (2) - -/* MEANING OF 'n_other' in the symbol record. - * - * If non-zero, the 'n_other' fields indicates either a leaf procedure or - * a system procedure, as follows: - * - * 1 <= n_other <= 32 : - * The symbol is the entry point to a system procedure. - * 'n_value' is the address of the entry, as for any other - * procedure. The system procedure number (which can be used in - * a 'calls' instruction) is (n_other-1). These entries come from - * '.sysproc' directives. - * - * n_other == N_CALLNAME - * the symbol is the 'call' entry point to a leaf procedure. - * The *next* symbol in the symbol table must be the corresponding - * 'bal' entry point to the procedure (see following). These - * entries come from '.leafproc' directives in which two different - * symbols are specified (the first one is represented here). - * - * - * n_other == N_BALNAME - * the symbol is the 'bal' entry point to a leaf procedure. - * These entries result from '.leafproc' directives in which only - * one symbol is specified, or in which the same symbol is - * specified twice. - * - * Note that an N_CALLNAME entry *must* have a corresponding N_BALNAME entry, - * but not every N_BALNAME entry must have an N_CALLNAME entry. - */ -#define N_CALLNAME ((char)-1) -#define N_BALNAME ((char)-2) - -/* i960 uses a custom relocation record. */ - -/* let obj-aout.h know */ -#define CUSTOM_RELOC_FORMAT 1 -/* let aout_gnu.h know */ -#define N_RELOCATION_INFO_DECLARED 1 -struct relocation_info - { - int r_address; /* File address of item to be relocated */ - unsigned - r_index:24, /* Index of symbol on which relocation is based*/ - r_pcrel:1, /* 1 => relocate PC-relative; else absolute - * On i960, pc-relative implies 24-bit - * address, absolute implies 32-bit. - */ - r_length:2, /* Number of bytes to relocate: - * 0 => 1 byte - * 1 => 2 bytes - * 2 => 4 bytes -- only value used for i960 - */ - r_extern:1, r_bsr:1, /* Something for the GNU NS32K assembler */ - r_disp:1, /* Something for the GNU NS32K assembler */ - r_callj:1, /* 1 if relocation target is an i960 'callj' */ - nuthin:1; /* Unused */ - }; - -/* No shared lib support, so we don't need to ensure externally - visible symbols can be overridden. */ -#define EXTERN_FORCE_RELOC 0 - -/* Makes no sense to use the difference of 2 arbitrary symbols - as the target of a call instruction. */ -#define TC_FORCE_RELOCATION_SUB_SAME(FIX, SEG) \ - (GENERIC_FORCE_RELOCATION_SUB_SAME (FIX, SEG) \ - || (FIX)->fx_tcbit \ - || TC_FORCE_RELOCATION (FIX)) - -/* reloc_callj() may replace a 'call' with a 'calls' or a - 'bal', in which cases it modifies *fixP as appropriate. - In the case of a 'calls', no further work is required. */ -extern int reloc_callj (struct fix *); - -#define TC_FORCE_RELOCATION_ABS(FIX) \ - (TC_FORCE_RELOCATION (FIX) \ - || reloc_callj (FIX)) - -#define TC_FORCE_RELOCATION_LOCAL(FIX) \ - (GENERIC_FORCE_RELOCATION_LOCAL (FIX) \ - || reloc_callj (FIX)) - -#ifdef OBJ_COFF - -/* We store the bal information in the sy_tc field. */ -#define TC_SYMFIELD_TYPE symbolS * - -#endif - -extern int i960_validate_fix (struct fix *, segT); -#define TC_VALIDATE_FIX(FIX,SEGTYPE,LABEL) \ - if (!i960_validate_fix (FIX, SEGTYPE)) goto LABEL - -#define tc_fix_adjustable(FIX) ((FIX)->fx_bsr == 0) - -#ifndef OBJ_ELF -/* Values passed to md_apply_fix sometimes include symbol values. */ -#define MD_APPLY_SYM_VALUE(FIX) tc_fix_adjustable (FIX) -#else -/* Values passed to md_apply_fix don't include the symbol value. */ -#define MD_APPLY_SYM_VALUE(FIX) 0 -#endif - -extern void brtab_emit (void); -#define md_end() brtab_emit () - -extern void tc_set_bal_of_call (symbolS *, symbolS *); - -extern struct symbol *tc_get_bal_of_call (symbolS *); - -extern void i960_handle_align (struct frag *); -#define HANDLE_ALIGN(FRAG) i960_handle_align (FRAG) -#define NO_RELOC -1 - -#define md_operand(x) - -extern const struct relax_type md_relax_table[]; -#define TC_GENERIC_RELAX_TABLE md_relax_table - -#define LINKER_RELAXING_SHRINKS_ONLY - -#define TC_FIX_TYPE struct { unsigned bsr : 1; } -#define fx_bsr tc_fix_data.bsr -#define TC_INIT_FIX_DATA(F) ((F)->tc_fix_data.bsr = 0) - -#endif diff --git a/gas/config/tc-m68k.c b/gas/config/tc-m68k.c index 13fb897..d73d154 100644 --- a/gas/config/tc-m68k.c +++ b/gas/config/tc-m68k.c @@ -5405,7 +5405,7 @@ md_estimate_size_before_relax (fragS *fragP, segT segment) return md_relax_table[fragP->fr_subtype].rlx_length; } -#if defined(OBJ_AOUT) | defined(OBJ_BOUT) +#if defined(OBJ_AOUT) /* the bit-field entries in the relocation_info struct plays hell with the byte-order problems of cross-assembly. So as a hack, I added this mach. dependent ri twiddler. Ugly, but it gets @@ -5433,7 +5433,7 @@ md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri) #endif -#endif /* OBJ_AOUT or OBJ_BOUT */ +#endif /* OBJ_AOUT */ #ifndef WORKING_DOT_WORD int md_short_jump_size = 4; diff --git a/gas/config/tc-score.c b/gas/config/tc-score.c index 146e86a..8b587c8 100644 --- a/gas/config/tc-score.c +++ b/gas/config/tc-score.c @@ -6217,8 +6217,7 @@ s3_s_score_lcomm (int bytes_p) *p = c; if ( -#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT) \ - || defined (OBJ_BOUT) || defined (OBJ_MAYBE_BOUT)) +#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) #ifdef BFD_ASSEMBLER (OUTPUT_FLAVOR != bfd_target_aout_flavour || (S_GET_OTHER (symbolP) == 0 && S_GET_DESC (symbolP) == 0)) && diff --git a/gas/config/tc-score7.c b/gas/config/tc-score7.c index 9cd6602..12271a3 100644 --- a/gas/config/tc-score7.c +++ b/gas/config/tc-score7.c @@ -6077,8 +6077,7 @@ s7_s_score_lcomm (int bytes_p) *p = c; if ( -#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT) \ - || defined (OBJ_BOUT) || defined (OBJ_MAYBE_BOUT)) +#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) #ifdef BFD_ASSEMBLER (OUTPUT_FLAVOR != bfd_target_aout_flavour || (S_GET_OTHER (symbolP) == 0 && S_GET_DESC (symbolP) == 0)) && diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c index c21192a..1994452 100644 --- a/gas/config/tc-sparc.c +++ b/gas/config/tc-sparc.c @@ -365,10 +365,6 @@ sparc_target_format (void) #endif #endif -#ifdef OBJ_BOUT - return "b.out.big"; -#endif - #ifdef OBJ_COFF #ifdef TE_LYNX return "coff-sparc-lynx"; -- cgit v1.1