From 1fed0ba155aff29779a9746bd789c6d769c2b1fe Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Sun, 17 Feb 2008 00:26:19 +0000 Subject: 2008-02-16 H.J. Lu * config/tc-i386.c (process_immext): Fix format. --- gas/config/tc-i386.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'gas/config') diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 9190fcf..03360e3 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -2402,20 +2402,19 @@ process_immext (void) if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0) { - /* SSE3 Instructions have the fixed operands with an opcode - suffix which is coded in the same place as an 8-bit immediate - field would be. Here we check those operands and remove them - afterwards. */ + /* SSE3 Instructions have the fixed operands with an opcode + suffix which is coded in the same place as an 8-bit immediate + field would be. Here we check those operands and remove them + afterwards. */ unsigned int x; for (x = 0; x < i.operands; x++) if (i.op[x].regs->reg_num != x) as_bad (_("can't use register '%s%s' as operand %d in '%s'."), - register_prefix, - i.op[x].regs->reg_name, - x + 1, - - i.tm.name); i.operands = 0; + register_prefix, i.op[x].regs->reg_name, x + 1, + i.tm.name); + + i.operands = 0; } /* These AMD 3DNow! and SSE2 Instructions have an opcode suffix -- cgit v1.1