From 80d49d6a1b865c84a8596da465db285cbbdfd1bb Mon Sep 17 00:00:00 2001 From: Kuan-Lin Chen Date: Wed, 24 Feb 2021 13:26:29 +0800 Subject: RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Add zba, zbb and zbc. gas/ * config/tc-riscv.c (ext_version_table): Add b, zba, zbb and zbc. (riscv_multi_subset_supports): Add INSN_CLASS_ZB*. * testsuite/gas/riscv/b-ext-64.s: Bitmanip test case. * testsuite/gas/riscv/b-ext-64.d: Likewise. * testsuite/gas/riscv/b-ext.s: Likewise. * testsuite/gas/riscv/b-ext.d: Likewise. include/ * opcode/riscv-opc.h: Support zba, zbb and zbc extensions. * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_ZB*. opcodes/ * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions. --- gas/config/tc-riscv.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'gas/config/tc-riscv.c') diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index bbf7052..429732f 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -139,6 +139,10 @@ static const struct riscv_ext_version ext_version_table[] = {"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0}, + {"zbb", ISA_SPEC_CLASS_DRAFT, 0, 93}, + {"zba", ISA_SPEC_CLASS_DRAFT, 0, 93}, + {"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93}, + /* Terminate the list. */ {NULL, 0, 0, 0} }; @@ -330,6 +334,15 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class) case INSN_CLASS_ZIHINTPAUSE: return riscv_subset_supports ("zihintpause"); + case INSN_CLASS_ZBB: + return riscv_subset_supports ("zbb"); + + case INSN_CLASS_ZBA: + return riscv_subset_supports ("zba"); + + case INSN_CLASS_ZBC: + return riscv_subset_supports ("zbc"); + default: as_fatal ("internal: unreachable"); return FALSE; -- cgit v1.1