From c4a23bf878f2e9a64034006c91596401faf6db3e Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Tue, 27 Aug 2019 12:08:21 +0100 Subject: Add support for the MVE VMOV instruction to the ARM assembler. This instruction copies the value of one vector register to another vector register. The patch also modifies the decoding of VORR instruction which is effecting decoding of VMOV instruction. gas * config/tc-arm.c (parse_neon_mov): Add check to accept vector register to both the arguments in VMOV instruction. * testsuite/gas/arm/mve-vmov-1.d: Modify. * testsuite/gas/arm/mve-vmov-1.s: Likewise. * testsuite/gas/arm/mve-vorr.d: Likewise. opcodes * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC. (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC. (print_insn_mve): Add condition to check Qm==Qn of VORR instruction. --- gas/config/tc-arm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'gas/config/tc-arm.c') diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 27c6f0e..9a367ca 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -6743,8 +6743,10 @@ parse_neon_mov (char **str, int *which_operand) inst.operands[i].present = 1; } } - else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, - &optype)) != FAIL) + else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, + &optype)) != FAIL) + || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype, + &optype)) != FAIL)) { /* Case 0: VMOV , Case 1: VMOV
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