From b7641ae1afaa39e31e70114f0ee9a295820709aa Mon Sep 17 00:00:00 2001
From: Jiawei <jiawei@iscas.ac.cn>
Date: Tue, 11 Jun 2024 21:59:00 +0800
Subject: RISC-V: Support S[sm]csrind extension csrs.

This patch supports RISC-V Smcsrind/Sscsrind privilege extension csrs.
Reuse csr 'smselect/siselect', 'mireg/sireg' and 'vsiselect,vsireg' csrs
in Smaia/Ssaia extension.

bfd/ChangeLog:

	* elfxx-riscv.c: New extensions.

gas/ChangeLog:

	* NEWS: Updated.
	* config/tc-riscv.c (enum riscv_csr_class): New extensions.
	(riscv_csr_address): Ditto.
	* testsuite/gas/riscv/csr-version-1p10.d: New csrs.
	* testsuite/gas/riscv/csr-version-1p10.l: Ditto.
	* testsuite/gas/riscv/csr-version-1p11.d: Ditto.
	* testsuite/gas/riscv/csr-version-1p11.l: Ditto.
	* testsuite/gas/riscv/csr-version-1p12.d: Ditto.
	* testsuite/gas/riscv/csr-version-1p12.l: Ditto.
	* testsuite/gas/riscv/csr.s: Ditto.
	* testsuite/gas/riscv/march-help.l: New extensions.

include/ChangeLog:

	* opcode/riscv-opc.h (CSR_MIREG2): New csr.
	(CSR_MIREG3): Ditto.
	(CSR_MIREG4): Ditto.
	(CSR_MIREG5): Ditto.
	(CSR_MIREG6): Ditto.
	(CSR_SIREG2): Ditto.
	(CSR_SIREG3): Ditto.
	(CSR_SIREG4): Ditto.
	(CSR_SIREG5): Ditto.
	(CSR_SIREG6): Ditto.
	(CSR_VSIREG2): Ditto.
	(CSR_VSIREG3): Ditto.
	(CSR_VSIREG4): Ditto.
	(CSR_VSIREG5): Ditto.
	(CSR_VSIREG6): Ditto.
	(DECLARE_CSR): Ditto.
---
 bfd/elfxx-riscv.c | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'bfd')

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 1fe7e5d..297d565 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1273,10 +1273,12 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zcb", "zca",	check_implicit_always},
   {"zcmp", "zca",	check_implicit_always},
   {"smaia", "ssaia",		check_implicit_always},
+  {"smscrind", "sscsrind",	check_implicit_always},
   {"smcntrpmf", "zicsr",	check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
   {"smepmp", "zicsr",		check_implicit_always},
   {"ssaia", "zicsr",		check_implicit_always},
+  {"sscsrind", "zicsr",		check_implicit_always},
   {"sscofpmf", "zicsr",		check_implicit_always},
   {"ssstateen", "zicsr",	check_implicit_always},
   {"sstc", "zicsr",		check_implicit_always},
@@ -1438,10 +1440,12 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
 static struct riscv_supported_ext riscv_supported_std_s_ext[] =
 {
   {"smaia",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"smcsrind",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smcntrpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smepmp",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssaia",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"sscsrind",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sscofpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sstc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
-- 
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