From 248bf6de04032c666cbbd8d3278efa60b6059660 Mon Sep 17 00:00:00 2001 From: Nelson Chu Date: Fri, 24 Nov 2023 15:46:56 +0800 Subject: RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0 SiFive has define as set of flexible instruction for extending vector coprocessor, it able to encoding opcode like .insn but with predefined format. List of instructions: sf.vc.x sf.vc.i sf.vc.vv sf.vc.xv sf.vc.iv sf.vc.fv sf.vc.vvv sf.vc.xvv sf.vc.ivv sf.vc.fvv sf.vc.vvw sf.vc.xvw sf.vc.ivw sf.vc.fvw sf.vc.v.x sf.vc.v.i sf.vc.v.vv sf.vc.v.xv sf.vc.v.iv sf.vc.v.fv sf.vc.v.vvv sf.vc.v.xvv sf.vc.v.ivv sf.vc.v.fvv sf.vc.v.vvw sf.vc.v.xvw sf.vc.v.ivw sf.vc.v.fvw Spec of Xsfvcp https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software Co-authored-by: Hau Hsu Co-authored-by: Kito Cheng --- bfd/elfxx-riscv.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'bfd') diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 58cc3a6..d6a3b6c 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1200,6 +1200,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"ssstateen", "zicsr", check_implicit_always}, {"sstc", "zicsr", check_implicit_always}, {"svadu", "zicsr", check_implicit_always}, + + {"xsfvcp", "zve32x", check_implicit_always}, {NULL, NULL, NULL} }; @@ -1378,6 +1380,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadvector", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadzvamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xsfvcp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0}, {NULL, 0, 0, 0, 0} }; @@ -2599,6 +2602,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadzvamo"); case INSN_CLASS_XVENTANACONDOPS: return riscv_subset_supports (rps, "xventanacondops"); + case INSN_CLASS_XSFVCP: + return riscv_subset_supports (rps, "xsfvcp"); default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); -- cgit v1.1