From 031254f2111f945ce6a1b8827e1a58ed7141fefe Mon Sep 17 00:00:00 2001 From: Andre Vieira Date: Mon, 15 Apr 2019 10:54:42 +0100 Subject: [binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI The patch is straightforward, it does the following: - support the new Tag_CPU_arch build attribute value, ie.: + declare the new value + update all the asserts forcing logic to be reviewed for new architectures + create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and add mapping from Tag_CPU_arch to it + teach readelf about new Tag_CPU_arch value - declare armv8.1-m.main as a supported architecture value - define Armv8.1-M Mainline in terms of feature bits available - tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature bits available - update architecture-specific logic in gas and bfd guarded by the asserts mentioned above. - tests for all the above ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme * archures.c (bfd_mach_arm_8_1M_MAIN): Define. * bfd-in2.h: Regenerate. * cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline. * elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline and update assert. (using_thumb2): Likewise. (using_thumb2_bl): Update assert. (arch_has_arm_nop): Likewise. (bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline. (tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging. *** binutils/ChangeLog *** 2019-04-15 Thomas Preud'homme * readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme * config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline Tag_CPU_arch build attribute value. Reindent. (get_aeabi_cpu_arch_from_fset): Update assert. (aeabi_set_public_attributes): Update assert for Tag_DIV_use logic. * testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test. *** include/ChangeLog *** 2019-04-15 Thomas Preud'homme * elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro. (MAX_TAG_CPU_ARCH): Set value to above macro. * opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro. (ARM_AEXT_V8_1M_MAIN): Likewise. (ARM_AEXT2_V8_1M_MAIN): Likewise. (ARM_ARCH_V8_1M_MAIN): Likewise. *** ld/ChangeLog *** 2019-04-15 Thomas Preud'homme * testsuite/ld-arm/attr-merge-13.attr: New test. * testsuite/ld-arm/attr-merge-13a.s: New test. * testsuite/ld-arm/attr-merge-13b.s: New test. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline. --- bfd/ChangeLog | 13 +++++++++++++ bfd/archures.c | 1 + bfd/bfd-in2.h | 1 + bfd/cpu-arm.c | 1 + bfd/elf32-arm.c | 49 +++++++++++++++++++++++++++++++++++++++++++------ 5 files changed, 59 insertions(+), 6 deletions(-) (limited to 'bfd') diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 506d54f..d9d1e9b 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,16 @@ +2019-04-15 Thomas Preud'homme + + * archures.c (bfd_mach_arm_8_1M_MAIN): Define. + * bfd-in2.h: Regenerate. + * cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline. + * elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline + and update assert. + (using_thumb2): Likewise. + (using_thumb2_bl): Update assert. + (arch_has_arm_nop): Likewise. + (bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline. + (tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging. + 2019-04-11 H.J. Lu * elf-linker-x86.h (elf_x86_cet_report): New. diff --git a/bfd/archures.c b/bfd/archures.c index 647cf0d..aaf2e11 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -341,6 +341,7 @@ DESCRIPTION .#define bfd_mach_arm_8R 24 .#define bfd_mach_arm_8M_BASE 25 .#define bfd_mach_arm_8M_MAIN 26 +.#define bfd_mach_arm_8_1M_MAIN 27 . bfd_arch_nds32, {* Andes NDS32. *} .#define bfd_mach_n1 1 .#define bfd_mach_n1h 2 diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 33a2940..4f63fe5 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -2274,6 +2274,7 @@ enum bfd_architecture #define bfd_mach_arm_8R 24 #define bfd_mach_arm_8M_BASE 25 #define bfd_mach_arm_8M_MAIN 26 +#define bfd_mach_arm_8_1M_MAIN 27 bfd_arch_nds32, /* Andes NDS32. */ #define bfd_mach_n1 1 #define bfd_mach_n1h 2 diff --git a/bfd/cpu-arm.c b/bfd/cpu-arm.c index 568fdbf..5a5da93 100644 --- a/bfd/cpu-arm.c +++ b/bfd/cpu-arm.c @@ -248,6 +248,7 @@ static const bfd_arch_info_type arch_info_struct[] = N (bfd_mach_arm_8R, "armv8-r", FALSE, & arch_info_struct[24]), N (bfd_mach_arm_8M_BASE, "armv8-m.base", FALSE, & arch_info_struct[25]), N (bfd_mach_arm_8M_MAIN, "armv8-m.main", FALSE, & arch_info_struct[26]), + N (bfd_mach_arm_8_1M_MAIN, "armv8.1-m.main", FALSE, & arch_info_struct[27]), N (bfd_mach_arm_unknown, "arm_any", FALSE, NULL) }; diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c index 03f3a59..23bfbcb 100644 --- a/bfd/elf32-arm.c +++ b/bfd/elf32-arm.c @@ -3835,13 +3835,14 @@ using_thumb_only (struct elf32_arm_link_hash_table *globals) arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch); /* Force return logic to be reviewed for each new architecture. */ - BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN); + BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN); if (arch == TAG_CPU_ARCH_V6_M || arch == TAG_CPU_ARCH_V6S_M || arch == TAG_CPU_ARCH_V7E_M || arch == TAG_CPU_ARCH_V8M_BASE - || arch == TAG_CPU_ARCH_V8M_MAIN) + || arch == TAG_CPU_ARCH_V8M_MAIN + || arch == TAG_CPU_ARCH_V8_1M_MAIN) return TRUE; return FALSE; @@ -3862,14 +3863,15 @@ using_thumb2 (struct elf32_arm_link_hash_table *globals) arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch); /* Force return logic to be reviewed for each new architecture. */ - BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN); + BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN); return (arch == TAG_CPU_ARCH_V6T2 || arch == TAG_CPU_ARCH_V7 || arch == TAG_CPU_ARCH_V7E_M || arch == TAG_CPU_ARCH_V8 || arch == TAG_CPU_ARCH_V8R - || arch == TAG_CPU_ARCH_V8M_MAIN); + || arch == TAG_CPU_ARCH_V8M_MAIN + || arch == TAG_CPU_ARCH_V8_1M_MAIN); } /* Determine whether Thumb-2 BL instruction is available. */ @@ -3881,7 +3883,7 @@ using_thumb2_bl (struct elf32_arm_link_hash_table *globals) bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch); /* Force return logic to be reviewed for each new architecture. */ - BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN); + BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN); /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */ return (arch == TAG_CPU_ARCH_V6T2 @@ -4101,7 +4103,7 @@ arch_has_arm_nop (struct elf32_arm_link_hash_table *globals) Tag_CPU_arch); /* Force return logic to be reviewed for each new architecture. */ - BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN); + BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN); return (arch == TAG_CPU_ARCH_V6T2 || arch == TAG_CPU_ARCH_V6K @@ -13719,6 +13721,8 @@ bfd_arm_get_mach_from_attributes (bfd * abfd) return bfd_mach_arm_8M_BASE; case TAG_CPU_ARCH_V8M_MAIN: return bfd_mach_arm_8M_MAIN; + case TAG_CPU_ARCH_V8_1M_MAIN: + return bfd_mach_arm_8_1M_MAIN; default: /* Force entry to be added for any new known Tag_CPU_arch value. */ @@ -14131,6 +14135,31 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out, T(V8M_MAIN), /* V8-M BASELINE. */ T(V8M_MAIN) /* V8-M MAINLINE. */ }; + const int v8_1m_mainline[] = + { + -1, /* PRE_V4. */ + -1, /* V4. */ + -1, /* V4T. */ + -1, /* V5T. */ + -1, /* V5TE. */ + -1, /* V5TEJ. */ + -1, /* V6. */ + -1, /* V6KZ. */ + -1, /* V6T2. */ + -1, /* V6K. */ + T(V8_1M_MAIN), /* V7. */ + T(V8_1M_MAIN), /* V6_M. */ + T(V8_1M_MAIN), /* V6S_M. */ + T(V8_1M_MAIN), /* V7E_M. */ + -1, /* V8. */ + -1, /* V8R. */ + T(V8_1M_MAIN), /* V8-M BASELINE. */ + T(V8_1M_MAIN), /* V8-M MAINLINE. */ + -1, /* Unused (18). */ + -1, /* Unused (19). */ + -1, /* Unused (20). */ + T(V8_1M_MAIN) /* V8.1-M MAINLINE. */ + }; const int v4t_plus_v6_m[] = { -1, /* PRE_V4. */ @@ -14151,6 +14180,10 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out, -1, /* V8R. */ T(V8M_BASE), /* V8-M BASELINE. */ T(V8M_MAIN), /* V8-M MAINLINE. */ + -1, /* Unused (18). */ + -1, /* Unused (19). */ + -1, /* Unused (20). */ + T(V8_1M_MAIN), /* V8.1-M MAINLINE. */ T(V4T_PLUS_V6_M) /* V4T plus V6_M. */ }; const int *comb[] = @@ -14165,6 +14198,10 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out, v8r, v8m_baseline, v8m_mainline, + NULL, + NULL, + NULL, + v8_1m_mainline, /* Pseudo-architecture. */ v4t_plus_v6_m }; -- cgit v1.1