From f3806e43d9c7e6ff84ac5245e37ed21827783f4c Mon Sep 17 00:00:00 2001
From: Ben Elliston <bje@au.ibm.com>
Date: Fri, 30 Apr 2004 06:46:53 +0000
Subject: * ppc-opc.c (powerpc_opcodes): Add "dbczl" instruction for
PPC970. [testsuite] * gas/ppc/power4.s: Add dcbz and dcbzl test cases.
* gas/ppc/power4.d: Update accordingly.
---
gas/testsuite/ChangeLog | 5 +++++
gas/testsuite/gas/ppc/power4.d | 5 ++++-
gas/testsuite/gas/ppc/power4.s | 4 ++++
opcodes/ChangeLog | 4 ++++
opcodes/ppc-opc.c | 22 +++++++++++-----------
5 files changed, 28 insertions(+), 12 deletions(-)
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 9ec1aff..1cfce64 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2004-04-30 Ben Elliston <bje@au.ibm.com>
+
+ * gas/ppc/power4.s: Add dcbz and dcbzl test cases.
+ * gas/ppc/power4.d: Update accordingly.
+
2004-04-26 H.J. Lu <hongjiu.lu@intel.com>
* gas/elf/elf.exp: Add group0a, group0b and group1 for section
diff --git a/gas/testsuite/gas/ppc/power4.d b/gas/testsuite/gas/ppc/power4.d
index 6094848..4a56a27 100644
--- a/gas/testsuite/gas/ppc/power4.d
+++ b/gas/testsuite/gas/ppc/power4.d
@@ -10,7 +10,7 @@ start address 0x0+
Sections:
Idx Name +Size +VMA +LMA +File off +Algn
- +0 \.text +0+b8 +0+ +0+ +.*
+ +0 \.text +0+c4 +0+ +0+ +.*
+CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+1 \.data +0+10 +0+ +0+ +.*
+CONTENTS, ALLOC, LOAD, DATA
@@ -99,3 +99,6 @@ Disassembly of section \.text:
+ac: 7c 72 00 26 mfcr r3,32
+b0: 7c 74 00 26 mfcr r3,64
+b4: 7c 78 00 26 mfcr r3,128
+ +b8: 7c 01 17 ec dcbz r1,r2
+ +bc: 7c 23 27 ec dcbzl r3,r4
+ +c0: 7c 05 37 ec dcbz r5,r6
diff --git a/gas/testsuite/gas/ppc/power4.s b/gas/testsuite/gas/ppc/power4.s
index 3514e63..f2a162d 100644
--- a/gas/testsuite/gas/ppc/power4.s
+++ b/gas/testsuite/gas/ppc/power4.s
@@ -68,6 +68,10 @@ dsym1:
mfcr 3,0x40
mfcr 3,0x80
+ dcbz 1, 2
+ dcbzl 3, 4
+ dcbz 5, 6
+
.section ".data"
usym0: .llong 0xcafebabe
usym1:
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ac27484..cd71b95 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2004-04-29 Ben Elliston <bje@au.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes): Add "dbczl" instruction for PPC970.
+
2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
* sh-dis.c (print_insn_sh): Print the value in constant pool
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 36fe454..e9df5de 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -1585,15 +1585,14 @@ extract_tbr (unsigned long insn,
/* An XRTRA_MASK, but with L bit clear. */
#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
-/* An X form comparison instruction. */
-#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
+/* An X form instruction with the L bit specified. */
+#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
/* The mask for an X form comparison instruction. */
#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
-/* The mask for an X form comparison instruction with the L field
- fixed. */
-#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
+/* The mask for an X form instruction with the L field fixed. */
+#define XOPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
/* An X form trap instruction with the TO field specified. */
#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
@@ -3146,10 +3145,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
-{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
-{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
+{ "cmpw", XOPL(31,0,0), XOPL_MASK, PPCCOM, { OBF, RA, RB } },
+{ "cmpd", XOPL(31,0,1), XOPL_MASK, PPC64, { OBF, RA, RB } },
{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
-{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
+{ "cmp", X(31,0), XOPL_MASK, PWRCOM, { BF, RA, RB } },
{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
@@ -3252,10 +3251,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
-{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
-{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
+{ "cmplw", XOPL(31,32,0), XOPL_MASK, PPCCOM, { OBF, RA, RB } },
+{ "cmpld", XOPL(31,32,1), XOPL_MASK, PPC64, { OBF, RA, RB } },
{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
-{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
+{ "cmpl", X(31,32), XOPL_MASK, PWRCOM, { BF, RA, RB } },
{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
@@ -4303,6 +4302,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
+{ "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
--
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