From de0addfbefefa300907b90954f18f1e49f95e6bd Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 24 Mar 2011 03:13:32 +0000 Subject: sim: bfin: always do 16bit sign extension with the SEARCH insn The Blackfin PRM does not cover this case, but the hardware is clear: even if the search criteria is not met (and thus a new 16bit value is loaded up into the accumulator), the accumulator undergoes 16bit sign extension. So simply reload the low signed 16bits in that case. Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger --- sim/bfin/ChangeLog | 5 +++++ sim/bfin/bfin-sim.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog index 900dc50..0e37ddd 100644 --- a/sim/bfin/ChangeLog +++ b/sim/bfin/ChangeLog @@ -1,5 +1,10 @@ 2011-03-23 Robin Getz + * bfin-sim.c (decode_dsp32alu_0): Set A1 to a1_lo when up_hi is false, + and set A0 to a0_lo when up_lo is false. + +2011-03-23 Robin Getz + * bfin-sim.c (decode_dsp32alu_0): Call saturate_s40_astat instead of saturate_s40, and use the v parameter to update the AV bit. Set the AC bit only when the final result is 0. diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c index c78fe1a..85e281a 100644 --- a/sim/bfin/bfin-sim.c +++ b/sim/bfin/bfin-sim.c @@ -5041,11 +5041,16 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) SET_AREG (1, src_hi); SET_DREG (dst1, PREG (0)); } + else + SET_AREG (1, a1_lo); + if (up_lo) { SET_AREG (0, src_lo); SET_DREG (dst0, PREG (0)); } + else + SET_AREG (0, a0_lo); } else illegal_instruction (cpu); -- cgit v1.1