From c31d7253d2d3bee10388a4908a4bffb0d0011c0a Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 21 Dec 2023 01:36:40 -0500 Subject: sim: rx: add missing break to memory write It doesn't seem like we want to keep executing the next block of code after processing the request. --- sim/rx/mem.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sim/rx/mem.c b/sim/rx/mem.c index 2cba4cb..83e2302 100644 --- a/sim/rx/mem.c +++ b/sim/rx/mem.c @@ -324,6 +324,7 @@ mem_put_byte (unsigned int address, unsigned char value) halt_pipeline_stats (); else reset_pipeline_stats (); + break; } #endif -- cgit v1.1