From b3fa92f12a83d284db3124e0992e15d1ff31a3d8 Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Mon, 18 Dec 2023 22:04:25 -0700 Subject: Yet another fix for mcore-sim (rotli) This came up testing the CRC optimization work from Mariam@RAU. Basically to optimize some CRC loops into table lookups or carryless multiplies, we may need to do a bit reflection, which on the mcore processor is done using a rotate instruction. Unfortunately the simulator implementation of rotates has the exact same problem as we saw with right shifts. The input value may have been sign extended from 32 to 64 bits. When we rotate the extended value, we get those sign extension bits and thus the wrong result. The fix is the same. Rather than using a "long", use a uint32_t for the type of the temporary. This fixes a handful of tests in the GCC testsuite: --- sim/mcore/interp.c | 2 +- sim/testsuite/mcore/rotli.s | 31 +++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 sim/testsuite/mcore/rotli.s diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c index 8bfb745..94e0a16 100644 --- a/sim/mcore/interp.c +++ b/sim/mcore/interp.c @@ -1015,7 +1015,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) case 0x38: case 0x39: /* xsr, rotli */ { unsigned imm = IMM5; - unsigned long tmp = gr[RD]; + uint32_t tmp = gr[RD]; if (imm == 0) { int32_t cbit; diff --git a/sim/testsuite/mcore/rotli.s b/sim/testsuite/mcore/rotli.s new file mode 100644 index 0000000..fd9a899 --- /dev/null +++ b/sim/testsuite/mcore/rotli.s @@ -0,0 +1,31 @@ +# check that lsri works correctly +# mach: mcore + +.include "testutils.inc" + + start + # Construct -1 + bmaski r2, 32 + + # Clear a couple bits + bclri r2, 0 + bclri r2, 1 + + # rotate by 16 + rotli r2, 16 + + # Construct 0xfffcffff + bmaski r1, 32 + bclri r1, 16 + bclri r1, 17 + + # Compare them, they should be equal + cmpne r2,r1 + jbt .L1 + pass +.L1: + fail + + + + -- cgit v1.1