From 6fbfdb27bc16883fe49b1bb9fb515729a24f2815 Mon Sep 17 00:00:00 2001 From: Peter Bergner Date: Tue, 28 Feb 2017 16:07:52 -0600 Subject: Backport addition of scv and rfscv P9 instructions. opcodes/ Apply from master. 2017-02-10 Nicholas Piggin * ppc-opc.c (powerpc_opcodes) : New mnemonics. gas/ Apply from master. 2017-02-10 Nicholas Piggin * testsuite/gas/ppc/power9.d : New tests. --- gas/ChangeLog | 7 +++++++ gas/testsuite/gas/ppc/power9.d | 3 +++ gas/testsuite/gas/ppc/power9.s | 3 +++ opcodes/ChangeLog | 7 +++++++ opcodes/ppc-opc.c | 4 +++- 5 files changed, 23 insertions(+), 1 deletion(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 50fcf52..f267472 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,10 @@ +2017-22-16 Peter Bergner + + Apply from master. + 2017-02-10 Nicholas Piggin + + * testsuite/gas/ppc/power9.d : New tests. + 2016-09-16 Peter Bergner Apply from master. diff --git a/gas/testsuite/gas/ppc/power9.d b/gas/testsuite/gas/ppc/power9.d index 31e4530..6bbe5e2 100644 --- a/gas/testsuite/gas/ppc/power9.d +++ b/gas/testsuite/gas/ppc/power9.d @@ -391,4 +391,7 @@ Disassembly of section \.text: .*: (ff d7 04 8e|8e 04 d7 ff) mffscrni f30,0 .*: (ff d7 1c 8e|8e 1c d7 ff) mffscrni f30,3 .*: (ff f8 04 8e|8e 04 f8 ff) mffsl f31 +.*: (01 00 00 44|44 00 00 01) scv 0 +.*: (e1 0f 00 44|44 00 0f e1) scv 127 +.*: (a4 00 00 4c|4c 00 00 a4) rfscv #pass diff --git a/gas/testsuite/gas/ppc/power9.s b/gas/testsuite/gas/ppc/power9.s index 469435d..27f1122 100644 --- a/gas/testsuite/gas/ppc/power9.s +++ b/gas/testsuite/gas/ppc/power9.s @@ -382,3 +382,6 @@ power9: mffscrni 30,0 mffscrni 30,3 mffsl 31 + scv 0 + scv 127 + rfscv diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 43841f5..62844a1 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2017-22-28 Peter Bergner + + Apply from master. + 2017-02-10 Nicholas Piggin + + * ppc-opc.c (powerpc_opcodes) : New mnemonics. + 2016-09-16 Peter Bergner Apply from master. diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 7003e0c..0ce5e79 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -441,7 +441,7 @@ const struct powerpc_operand powerpc_operands[] = #define L1 L0 + 1 { 0x1, 21, insert_l1, extract_l1, 0 }, - /* The LEV field in a POWER SVC form instruction. */ + /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */ #define SVC_LEV L1 + 1 { 0x7f, 5, NULL, NULL, 0 }, @@ -4185,6 +4185,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, +{"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}}, {"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, {"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}}, {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}}, @@ -4434,6 +4435,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}}, {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}}, +{"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}}, {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}}, {"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}}, -- cgit v1.1