From 3f946aa82518e878aea2cba4b6a9bcc651412c5c Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sun, 11 Oct 2015 03:32:11 -0400 Subject: sim: bfin: handle negative left saturated shifts as ashifts [BZ #18407] When handling left saturated ashifts with negative immediates, they should be treated as right ashifts. This matches hardware behavior. Reported-by: Igor Rayak --- sim/bfin/ChangeLog | 6 ++++++ sim/bfin/bfin-sim.c | 6 +++++- sim/testsuite/sim/bfin/ChangeLog | 5 +++++ sim/testsuite/sim/bfin/ashift_left.s | 17 +++++++++++++++++ 4 files changed, 33 insertions(+), 1 deletion(-) create mode 100644 sim/testsuite/sim/bfin/ashift_left.s diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog index d0e91b3..2e62a74 100644 --- a/sim/bfin/ChangeLog +++ b/sim/bfin/ChangeLog @@ -1,3 +1,9 @@ +2015-10-11 Mike Frysinger + + PR sim/18407 + * bfin-sim.c (decode_dsp32shiftimm_0): Call ashiftrt when count + is less than 0. + 2015-06-24 Mike Frysinger * interp.c (trace_register): Delete. diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c index 8b19ead..b6acb4e 100644 --- a/sim/bfin/bfin-sim.c +++ b/sim/bfin/bfin-sim.c @@ -6083,7 +6083,11 @@ decode_dsp32shiftimm_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) int count = imm6 (immag); TRACE_INSN (cpu, "R%i = R%i << %i (S);", dst0, src1, count); - STORE (DREG (dst0), lshift (cpu, DREG (src1), count, 32, 1, 1)); + + if (count < 0) + STORE (DREG (dst0), ashiftrt (cpu, DREG (src1), -count, 32)); + else + STORE (DREG (dst0), lshift (cpu, DREG (src1), count, 32, 1, 1)); } else if (sop == 2 && sopcde == 2) { diff --git a/sim/testsuite/sim/bfin/ChangeLog b/sim/testsuite/sim/bfin/ChangeLog index 89d2833..4fc604f 100644 --- a/sim/testsuite/sim/bfin/ChangeLog +++ b/sim/testsuite/sim/bfin/ChangeLog @@ -1,3 +1,8 @@ +2015-10-11 Mike Frysinger + + PR sim/18407 + * ashift_left.s: New test. + 2013-12-07 Mike Frysinger * run-tests.sh: Add +x file mode. diff --git a/sim/testsuite/sim/bfin/ashift_left.s b/sim/testsuite/sim/bfin/ashift_left.s new file mode 100644 index 0000000..04cfa40 --- /dev/null +++ b/sim/testsuite/sim/bfin/ashift_left.s @@ -0,0 +1,17 @@ +# Blackfin testcase for left ashift +# Dreg = Dreg << imm (S); +# mach: bfin + + .include "testutils.inc" + + .macro test in:req, shift:req, out:req, opt + imm32 r0, \in; + r1 = r0 >>> \shift \opt; + CHECKREG r1, \out; + .endm + + start + +test 2, 1, 1, (S); + + pass -- cgit v1.1