From 37b329352042564a5b4c41c1244fc04af8c3cb04 Mon Sep 17 00:00:00 2001 From: Jie Zhang Date: Fri, 26 Sep 2008 04:49:17 +0000 Subject: * config/bfin-parse.y (asm_1): Fix reduce/reduce conflicts. --- gas/ChangeLog | 4 ++++ gas/config/bfin-parse.y | 22 ++++++++++------------ 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 3d023df..eb8240d 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,7 @@ +2008-09-26 Jie Zhang + + * config/bfin-parse.y (asm_1): Fix reduce/reduce conflicts. + 2008-09-24 Richard Henderson * dw2gencfi.c (DWARF2_ADDR_SIZE): Provide default. diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y index 283b813..f91224e 100644 --- a/gas/config/bfin-parse.y +++ b/gas/config/bfin-parse.y @@ -1932,22 +1932,20 @@ asm_1: else return yyerror ("Bad shift value or register"); } - | HALF_REG ASSIGN HALF_REG LESS_LESS expr - { - if (IS_UIMM ($5, 4)) - { - notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n"); - $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3)); - } - else - return yyerror ("Bad shift value"); - } | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod { if (IS_UIMM ($5, 4)) { - notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n"); - $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3)); + if ($6.s0) + { + notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n"); + $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3)); + } + else + { + notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n"); + $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3)); + } } else return yyerror ("Bad shift value"); -- cgit v1.1